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2106 Commits

Author SHA1 Message Date
Florent Kermarrec 71a719be44 soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
Florent Kermarrec 9032665750 soc/interconnect/wishbonebridge: fix import 2016-03-16 19:34:50 +01:00
Florent Kermarrec d7112efdba soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now) 2016-03-16 19:33:29 +01:00
Florent Kermarrec 39aacf2df4 soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring 2016-03-16 19:33:00 +01:00
Florent Kermarrec e0e2427795 soc: replace all Sink/Source with stream.Endpoint 2016-03-16 18:05:57 +01:00
Florent Kermarrec c860581b86 soc/interconnect/stream: use new Converter/StrideConverter 2016-03-16 17:00:58 +01:00
Florent Kermarrec 8c272c1f6f soc/interconnect/stream: fix missing param 2016-03-16 16:21:32 +01:00
Florent Kermarrec cb47373383 soc/interconnect/stream: remove packetized parameter and use of sop 2016-03-16 11:54:28 +01:00
Florent Kermarrec 44a5b95281 soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter) 2016-03-15 15:52:57 +01:00
Florent Kermarrec a016ededa0 soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert) 2016-03-04 20:56:05 +01:00
Florent Kermarrec 042c36ee1b soc/tools/litex_term: continue cleanup 2016-02-19 17:44:25 +01:00
Florent Kermarrec 2fa848c15f soc/tools/litex_term: continue cleanup 2016-02-19 14:35:18 +01:00
Florent Kermarrec 247ecc5d8a soc/tools/litex_term: continue cleanup 2016-02-19 13:38:34 +01:00
Florent Kermarrec ed2e623994 soc/tools/litex_term: remove write_exact, use more bytes 2016-02-19 00:20:10 +01:00
Florent Kermarrec 4bdefbdfba soc/tools/litex_term: remove character function 2016-02-19 00:02:38 +01:00
Florent Kermarrec 5b8566d20f soc/tools/litex_term: replace get_file_data with f.read() 2016-02-18 23:55:41 +01:00
Florent Kermarrec 68c2d3b7a0 soc/tools/remove: fix import 2016-02-18 12:55:18 +01:00
Florent Kermarrec fd2997bf4a build/xilinx: cleanup Vivado/ISE special_overrides 2016-02-18 00:36:53 +01:00
Florent Kermarrec 8ee3874088 soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master 2016-02-18 00:11:25 +01:00
Florent Kermarrec 34b45e3618 gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework) 2016-02-11 22:54:26 +01:00
Florent Kermarrec 2218ece98a soc/interconnect/stream: fix merge issue (missing params connect) 2016-02-01 00:08:27 +01:00
Florent Kermarrec 6c71811138 soc/tools/litex_term: also rename inside file 2016-01-16 21:26:33 +01:00
Florent Kermarrec 601c91a3e2 soc/tools: rename to litex_term, litex_server, litex_client 2016-01-16 21:22:21 +01:00
Florent Kermarrec 162900144a soc/tools/remove_server: cleanup 2016-01-16 21:12:19 +01:00
Florent Kermarrec b856b54720 soc/tools/flterm: get rid of serial.tools.miniterm import and fix echo on linux 2016-01-16 21:05:03 +01:00
Florent Kermarrec 002508a69a soc/integration: return vns with soc and builder 2016-01-14 17:15:39 +01:00
Florent Kermarrec 2c32791a28 soc/software/bios/main: add capability to configure TEST_USER_ABORT_DELAY 2016-01-14 16:53:04 +01:00
Florent Kermarrec 492f276247 soc/software/bios/main: give priority to romboot over serialboot/netboot 2016-01-14 16:46:42 +01:00
Florent Kermarrec 9913da5ac9 boards/targets: change mode (add +x) 2016-01-01 18:37:20 +01:00
Florent Kermarrec 7b879b36c6 soc/tools/remove/server: avoid closing server when client closes connection 2015-12-27 22:33:08 +01:00
Florent Kermarrec 0498a31818 some cleanup 
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
 2015-12-27 13:09:58 +01:00
Florent Kermarrec 219fbef26c soc/tools/remove/client: set socket timeout to 5s 2015-12-27 11:26:58 +01:00
Florent Kermarrec 6ea65f957c soc/interconnect/stream: expose Endpoint 2015-12-19 21:49:45 +01:00
Florent Kermarrec 6a4e3bb5c0 build/xilinx/vivado: use build_name as top in synth_design 2015-12-09 11:40:27 +01:00
Florent Kermarrec 3191533889 soc/software/libnet: add debug defines on microudp 2015-12-07 12:03:36 +01:00
Florent Kermarrec 4fed1cc7a7 soc/integration/builder: move csr_csv generation outside of generate include 
we mostly use csr_csv for designs without CPU
 2015-12-03 15:16:22 +01:00
Florent Kermarrec 90f03133ef build/sim/verilator: add toolchain_path parameter 2015-12-02 15:35:55 +01:00
Florent Kermarrec e8262ed447 build: pass build_name to get_verilog (same name for top module and top level file) 2015-12-02 14:18:09 +01:00
Florent Kermarrec b7a1888a36 gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus) 
We will remove that when we will be using new migen simulator
 2015-12-02 14:16:23 +01:00
Florent Kermarrec 646d3b19b4 boards/nexys_video: use ethernet constraints similar to kc705 2015-12-01 11:50:05 +01:00
Florent Kermarrec ca6b9aa6e3 boards/targets: add default rom/ram configuration for arty 2015-12-01 10:20:16 +01:00
Florent Kermarrec e5d35ccb6d boards/targets: add nexys_video 2015-12-01 10:19:41 +01:00
Florent Kermarrec 4bfd1fdce6 boards/plaforms: fix IOStandard of eth_rst_n 2015-11-30 22:27:40 +01:00
Florent Kermarrec b6a6b5d540 boards/platforms: add cpu_reset to nexys_video and some fixes around DDR3 2015-11-30 21:53:01 +01:00
Florent Kermarrec 5694dca0fc boards/platforms: add hdmi_in/hdmi_out/ethernet/dram to nexys_video 2015-11-30 20:46:57 +01:00
Florent Kermarrec 7e1df951ba boards/platforms: add nexys_video (basic) 2015-11-30 20:25:00 +01:00
Florent Kermarrec a716c562f0 gen/build: use name_override for all IOs defined in Platform file (avoid random naming of IOs) 2015-11-30 18:26:33 +01:00
Florent Kermarrec 53c86e34f4 build: ensure we return to working directory after building 2015-11-30 13:33:39 +01:00
Florent Kermarrec f6aeb6e41a soc/interconnect/stream: improve Pipeline to allow passing endpoints 2015-11-28 18:31:47 +01:00
Florent Kermarrec d85d2b7b9b soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field 2015-11-27 20:14:01 +01:00
Florent Kermarrec c0539fff3e boards: add new digilent arty 2015-11-27 00:29:30 +01:00
Florent Kermarrec c24727ab4c soc/integration: allow using builder with soc.cpu_type == None 2015-11-26 17:44:50 +01:00
Florent Kermarrec 7298fff1e6 soc/interconnect/stream_packet: fix Counter removing 2015-11-24 20:30:53 +01:00
Florent Kermarrec 8ebffc563a soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister 2015-11-23 19:13:37 +01:00
Florent Kermarrec 254504e73f soc/integration/builder: export constants and memory_regions with csr_csv 2015-11-23 19:12:58 +01:00
Florent Kermarrec f6a2d5847a soc/tools/remote/client: make csr_csv parameter optional and default value to None 2015-11-23 18:39:28 +01:00
Florent Kermarrec 6f4dd14ffa soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant 2015-11-23 11:08:04 +01:00
Florent Kermarrec cb22a207f1 build/generic_platform: add support for int parameter for Pins (useful for core generation) 2015-11-19 14:57:09 +01:00
Florent Kermarrec 8056653004 soc/tools/remote/server: add --debug parameter 2015-11-17 15:43:10 +01:00
Florent Kermarrec 6870707620 soc/tools/remoter/server: fix exit on KeyboardInterrupt 2015-11-17 15:31:23 +01:00
Florent Kermarrec 8ff31557c6 soc/tools/remoter/server: add some printfs 2015-11-17 15:18:46 +01:00
Florent Kermarrec 1a92489555 soc/tools/remote: add comm_pcie and comm_udp (to be tested) 2015-11-17 15:07:00 +01:00
Florent Kermarrec d6fdd76930 soc/tools/remote: small cleanup and remove csr_data_width from server side 2015-11-17 11:35:22 +01:00
Florent Kermarrec 71483b8935 soc/tools: initialize wishbone remote control (for now only uart) 2015-11-17 01:05:52 +01:00
Florent Kermarrec 1cde84dccf soc/cores/uart remove software (will be re-written and will move to soc/tools) 2015-11-16 17:07:22 +01:00
Florent Kermarrec 1f80bb9561 soc/interconnect/stream_packet: remove Counter 2015-11-16 16:53:23 +01:00
Florent Kermarrec ec35290c45 soc/interconnect/wishbonebridge: remove Counter 2015-11-16 16:48:37 +01:00
Florent Kermarrec 6fd0b73817 build: remove edif support 2015-11-16 16:26:38 +01:00
Florent Kermarrec e407a1cdda gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign 2015-11-16 16:18:09 +01:00
Florent Kermarrec 2f52d364af soc/interconnect/stream/SyncFIFO: expose fifo level 2015-11-16 16:11:31 +01:00
Florent Kermarrec 7ed2576ce1 soc/integration/cpu_interface: add bases, constants and memories output to csv files 2015-11-15 00:04:44 +01:00
Florent Kermarrec af909b43d5 soc/cores/uart: add UARTWishboneBridgeDriver software 2015-11-14 21:23:20 +01:00
Florent Kermarrec 3a2e6117f4 soc/interconnect/stream: add Cast and others small fixes 2015-11-14 12:17:09 +01:00
Florent Kermarrec 041483dbe1 soc/integration/builder: only copy Makefiles when not using symlinks 2015-11-14 03:36:46 +01:00
Florent Kermarrec a2aa5726bf soc/cores: remove liteeth_mini and use liteeth 2015-11-14 03:22:43 +01:00
Florent Kermarrec 16ba646b1b add TODOs 2015-11-14 03:15:10 +01:00
Florent Kermarrec cf4c7da2e7 fix soc/integration/soc_core.py 2015-11-14 02:44:12 +01:00
Florent Kermarrec 032f5a9620 soc/interconnect: add stream_sim 2015-11-14 00:43:49 +01:00
Florent Kermarrec ba959c832d soc/interconnect: rename packet to stream_packet 2015-11-14 00:42:58 +01:00
Florent Kermarrec fc3ffe87ac for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
Florent Kermarrec ae3d54499a litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented 2015-11-13 14:44:16 +01:00
Florent Kermarrec 7d6cee6751 soc/interconnect/stream: add BufferizeEndpoints 2015-11-12 18:54:15 +01:00
Florent Kermarrec 83427c87cd soc/interconnect/stream: add Pipeline 2015-11-12 01:41:23 +01:00
Florent Kermarrec 81c6facca2 soc/interconnect/stream: reintroduce params 2015-11-12 01:12:15 +01:00
Florent Kermarrec f6b30fcae2 soc/interconnect: add packet 2015-11-12 00:54:40 +01:00
Florent Kermarrec 525da89c7d soc/interconnect: add wishbonebridge and uart bridge 2015-11-12 00:52:36 +01:00
Florent Kermarrec 89b189ce4a soc/interconnect/stream: reintroduce PipelinedActor/Buffer 2015-11-12 00:51:32 +01:00
Florent Kermarrec 194e6137ae soc/integration/soc_core: add support for SoCs without CPU 2015-11-12 00:50:23 +01:00
Florent Kermarrec c076c2cbd6 boards/targets: remove papilio_pro/pipistrello 2015-11-11 17:38:03 +01:00
Florent Kermarrec 352cb91688 soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default 
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
 2015-11-11 17:37:28 +01:00
Florent Kermarrec 1cec0f8086 boards/targets/sim: add ethernet support 2015-11-11 14:23:39 +01:00
Florent Kermarrec 1f6983da2c soc/cores/liteeth_mini: add phy model for verilator simulation 2015-11-11 14:22:27 +01:00
Florent Kermarrec 481163b233 soc/cores: reintroduce liteeth_mini (until we switch to liteeth) 2015-11-11 14:01:48 +01:00
Florent Kermarrec 714a3d88e2 add LICENSE, update copyrights, add Migen install instructions 2015-11-11 13:22:39 +01:00
Florent Kermarrec bda196fbc8 soc/software/bios/sdram: split memtest and allow external #define of memtest sizes 2015-11-11 13:10:03 +01:00
Florent Kermarrec 619cd8e695 avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules 2015-11-11 12:10:55 +01:00
Florent Kermarrec 3f43a49382 soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
 2015-11-10 16:51:51 +01:00
Florent Kermarrec 3297210e48 boards/targets/sim: get SDRAM working in simulation with sdram/model 2015-11-10 12:57:23 +01:00
Florent Kermarrec 4afe4a07e4 soc/software: remove memtest (should be re-written) 2015-11-10 12:22:08 +01:00
Florent Kermarrec 6764c06b62 soc/sofware: remove libdyld 2015-11-10 12:21:23 +01:00
Florent Kermarrec f72e172ac3 soc/software: remove libunwind 2015-11-10 12:16:34 +01:00
Florent Kermarrec 85e6716b6b litex/build/xilinx/programmer: remove UrJTAG and Adept 2015-11-10 12:01:25 +01:00
Florent Kermarrec a775672314 litex: get verilator simulation working and add sim target as example 2015-11-07 23:51:37 +01:00
Florent Kermarrec 6a0f85dc42 litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
Florent Kermarrec 637634f312 import migen in litex/gen 2015-11-07 12:22:32 +01:00
Florent Kermarrec b028569784 import misoc in litex/soc 2015-11-07 12:19:30 +01:00