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Author SHA1 Message Date
Florent Kermarrec
8f67f1157d soc/soc_core: cleanup, remove some unused attributes 2020-02-07 15:19:02 +01:00
Florent Kermarrec
2c6e5066a7 soc: move SoCController from soc_core to soc 2020-02-07 14:52:53 +01:00
Florent Kermarrec
848fa20d1e soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler 2020-02-07 13:25:54 +01:00
Florent Kermarrec
39458c92eb soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined 2020-02-06 19:50:44 +01:00
Florent Kermarrec
1eff0799a4 soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined 2020-02-06 18:50:17 +01:00
Florent Kermarrec
8bc420679a soc/integration: initial adaptation to new SoC class 2020-02-06 18:21:13 +01:00
Florent Kermarrec
1d70ef6958 soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) 2020-02-06 17:58:01 +01:00
Florent Kermarrec
62f3537db0 soc/cores: rename spiopi to spi_opi 2020-02-06 17:08:00 +01:00
Florent Kermarrec
f58e8188b7 soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 17:00:04 +01:00
enjoy-digital
c2c80b5d0a
Merge pull request #378 from betrusted-io/merge_ip 
Request to merge I2S and SPIOPI cores
 2020-02-06 16:29:33 +01:00
bunnie
98e46c2708 reduce indents 2020-02-06 21:55:44 +08:00
Florent Kermarrec
6baa07a69b soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC 2020-02-06 11:06:41 +01:00
bunnie
d2b394a9be update doc comments on events for i2s 2020-02-06 17:58:02 +08:00
bunnie
416afd3109 add doc comment for event 2020-02-06 17:56:21 +08:00
bunnie
33d9e45a8b fix formatting on spiopi 
Pycharm really butchered the code when I did a copy-and-paste...
it has questionable default formatting preferences.
 2020-02-06 17:54:26 +08:00
Florent Kermarrec
9b11e9192d cpu/vexriscv: update submodule 2020-02-06 10:50:35 +01:00
bunnie
cc6ed667df Request to merge I2S and SPIOPI cores 2020-02-06 17:25:00 +08:00
Sean Cross
ae085782ae doc: add lxsocdoc.md (README from lxsocdoc repository) 2020-02-05 11:06:57 +01:00
enjoy-digital
5ff02e23a0
Merge pull request #375 from xobs/add-lxsocdoc 
Add lxsocdoc
 2020-02-05 10:15:21 +01:00
Florent Kermarrec
1944d8d9d0 bios/main: add LiteX tagline 2020-02-04 19:14:23 +01:00
enjoy-digital
40cddca933
Merge pull request #376 from antmicro/build-sim-do-not-override-C-LD-FLAGS 
build/sim: allow to use environment's {C,LD}FLAGS
 2020-02-04 18:19:33 +01:00
Mariusz Glebocki
90fe585003 build/sim: allow to use environment's {C,LD}FLAGS 
There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
 2020-02-04 17:31:31 +01:00
Sean Cross
58598d4fda integration: svd: move svd generation to export 
It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h.  This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-04 23:49:08 +08:00
Sean Cross
73ed7e564c soc: doc: use sphinx toctree as it was intended 
The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely.  This patch causes it to be used correctly,
which removes the need for double-including various sections.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-04 20:34:10 +08:00
Sean Cross
7c3bc0b09f litex-doc: initial merge of lxsocdoc 
lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.

This merges the existing lxsocdoc distribution into the `soc/doc` directory.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-04 20:14:41 +08:00
enjoy-digital
bd6fd3da55
Merge pull request #373 from antmicro/l2-reverse 
tools/litex_sim: use l2_reverse flag
 2020-02-03 12:55:48 +01:00
Piotr Binkowski
f3b068e2ee tools/litex_sim: use l2_reverse flag 2020-02-03 12:03:57 +01:00
Florent Kermarrec
3350d33f9c wishbone/Cache: add reverse parameter 2020-01-31 19:31:33 +01:00
Florent Kermarrec
eff9caee6a soc_sdram: add l2_reverse parameter 2020-01-31 19:18:07 +01:00
enjoy-digital
6e5b47f4c6
Merge pull request #370 from Disasm/fixes 
Small fixes
 2020-01-31 18:27:26 +01:00
Vadim Kaushan
de88ed282a
Fix argument descriptions 2020-01-31 18:54:25 +03:00
Vadim Kaushan
eb49ec217e
Pass --csr-json to the Builder 2020-01-31 18:53:50 +03:00
Florent Kermarrec
b69f2993e4 soc_core: add UART bridge support (simplify having to do it externally) 2020-01-31 15:12:18 +01:00
Florent Kermarrec
7a6c04db9e build/altera/quartus: fix fmt_r typo 2020-01-30 13:55:13 +01:00
Florent Kermarrec
c6b9676db8 cpu/minerva: update (use new nMigen API) 2020-01-30 13:42:02 +01:00
Florent Kermarrec
9d2894727e inteconnect/stream: use PipeValid implementation for Buffer 2020-01-30 09:36:04 +01:00
Florent Kermarrec
1c88c0f896 inteconnect/stream: cleanup 2020-01-30 09:32:04 +01:00
enjoy-digital
cafd9c358a
Merge pull request #366 from gsomlo/gls-csr-followup 
software, integration/export: (re-)expose CSR subregister accessors
 2020-01-30 08:18:12 +01:00
Gabriel Somlo
ff2775c264 software, integration/export: (re-)expose CSR subregister accessors 
Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.

This restores downstream ability to override CSR handling at the
subregister accessor level.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-01-29 14:29:24 -05:00
Florent Kermarrec
f3f9808d1f interconnect/stream: add PipeValid and PipeWait to cut timing paths. 2020-01-29 18:27:29 +01:00
Florent Kermarrec
b22ad1acfb build/xilinx/vivado: improve readability of generated tcl/xdc files 2020-01-29 16:27:18 +01:00
Florent Kermarrec
7bc34a9bc7 integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). 
When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
 2020-01-29 08:31:41 +01:00
enjoy-digital
b4b56db4e3
Merge pull request #363 from antmicro/litex-sim-ddr4 
tools/litex_sim: add ddr4 PhySettings
 2020-01-28 15:36:24 +01:00
Piotr Binkowski
c02dd5e8f9 tools/litex_sim: add ddr4 PhySettings 2020-01-28 14:28:24 +01:00
Florent Kermarrec
0820adbda1 tools/litex_sim: add --sdram-init parameter 2020-01-27 21:30:13 +01:00
Florent Kermarrec
01ae10b803 software/bios: revert M-Labs MiSoC copyright. 2020-01-27 13:12:37 +01:00
Florent Kermarrec
ea5ef8c1be README: update copyright year and make sure LICENSE/README both mention MiSoC 2020-01-27 12:15:11 +01:00
Florent Kermarrec
95cfa6a82c platforms/netv2: add pcie pins 2020-01-27 08:25:57 +01:00
enjoy-digital
f9bc98ed4c
Merge pull request #359 from gregdavill/bios_ddr3_ecp5 
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
 2020-01-26 11:44:14 +01:00
Greg Davill
1f43906236 soc/software/bios/sdram: ECP5 move strobe dly_sel 2020-01-26 09:55:38 +10:30