Florent Kermarrec
54fb3a61cd
test/test_targets: use uart-name=stub.
2020-02-29 11:07:10 +01:00
Florent Kermarrec
59e99bfbcd
soc/uart: add configurable UART FIFO depth.
2020-02-28 22:34:11 +01:00
Florent Kermarrec
9199306a65
cores/uart: cleanup
2020-02-28 22:12:05 +01:00
Florent Kermarrec
ea8563339f
soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
2020-02-28 22:03:40 +01:00
Florent Kermarrec
12a7528667
interconnect/stream/SyncFIFO: allow depth down to 0.
2020-02-28 21:54:02 +01:00
Florent Kermarrec
9e31bf357e
interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.
2020-02-28 16:33:18 +01:00
Florent Kermarrec
1e0e96f9a0
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
2020-02-28 16:25:09 +01:00
Florent Kermarrec
6be7e9c33d
interconnect/axi: set default data_width/address_width to 32-bit.
2020-02-28 13:20:01 +01:00
Florent Kermarrec
8e1d528663
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:48:48 +01:00
Florent Kermarrec
a7c5dd5d3e
cores/gpio: use separate TSTriple for each bit.
...
This fixes per bit OE control.
2020-02-28 09:10:28 +01:00
Florent Kermarrec
400492e234
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.
2020-02-28 08:32:29 +01:00
Florent Kermarrec
c4fd6a7f2f
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 13:00:35 +01:00
Florent Kermarrec
78a3223573
software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling.
...
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:
Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00
After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10
2020-02-27 12:26:27 +01:00
Florent Kermarrec
eab5161d47
boards: keep in sync with LiteX-boards
2020-02-27 11:18:14 +01:00
Florent Kermarrec
935e4effd2
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
2020-02-26 15:13:29 +01:00
Florent Kermarrec
d324c54eee
integration/soc: -x on soc.py
2020-02-26 14:43:01 +01:00
Florent Kermarrec
ee27a9e534
soc/cores/bitbang: fix missing self.comb on miso.
2020-02-25 15:57:14 +01:00
enjoy-digital
a2d6986910
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins
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tools: litex_gen: fix missing UART pins
2020-02-25 15:53:13 +01:00
Florent Kermarrec
e2aebb427e
software: disable LTO with LM32 (not supported by old GCC versions easily available).
2020-02-25 15:32:36 +01:00
enjoy-digital
9e70fcf8ba
Merge pull request #401 from antmicro/enable-lto
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software: enable link time optimization (LTO)
2020-02-25 15:32:12 +01:00
Jan Kowalewski
75b000a32f
tools: litex_gen: fix missing UART pins
2020-02-25 14:24:29 +01:00
Tim 'mithro' Ansell
718a65c3c9
software: enable link time optimization (LTO)
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Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
2020-02-24 16:12:21 +01:00
enjoy-digital
9521f2ff80
Merge pull request #400 from Xiretza/ecp5-pll-freqfix
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Fix ECP5PLL VCO frequency range
2020-02-24 14:49:35 +01:00
Xiretza
7a87d4e262
Fix ECP5PLL VCO frequency range
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See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
2020-02-24 14:39:59 +01:00
Florent Kermarrec
0c7e0bf025
integration/soc: improve presentation of SoCLocHandler's locations.
2020-02-24 13:37:38 +01:00
Florent Kermarrec
0042a02807
interconnect/axi: remove bus_name on connect_to_pads
2020-02-24 13:24:32 +01:00
Florent Kermarrec
5aba1fe824
tools/litex_gen: add bus parameter and AXI (Lite) support.
2020-02-24 12:49:42 +01:00
Florent Kermarrec
a3584147a5
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:52 +01:00
Florent Kermarrec
d86db6f12b
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:20 +01:00
Florent Kermarrec
18c57a64a3
tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.
2020-02-24 10:25:18 +01:00
enjoy-digital
0083e0978b
Merge pull request #396 from antmicro/external-wb
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Add a script that allows to generate standalone cores
2020-02-24 10:01:16 +01:00
enjoy-digital
017c91a4be
Merge pull request #397 from gsomlo/gls-csr-volatile
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Add 'volatile' qualifier to new CSR accessors
2020-02-21 21:08:22 +01:00
Gabriel Somlo
173117ad4b
Add 'volatile' qualifier to new CSR accessors
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Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.
Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.
No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
2020-02-21 14:10:13 -05:00
Piotr Binkowski
9e2aede8a8
tools: add script for extracting wishbone cores
2020-02-21 16:33:26 +01:00
Karol Gugala
79a14001b0
axi: add to_pads method
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-02-21 12:22:18 +01:00
Jan Kowalewski
e0bcb57d3d
wishbone: add extracting module signals to the top
2020-02-21 11:20:32 +01:00
Florent Kermarrec
485934edc9
doc/socdoc: fix example
2020-02-20 19:47:15 +01:00
Florent Kermarrec
53ee9a5e05
cpu/blackparrot: first cleanup pass
2020-02-20 18:50:13 +01:00
Florent Kermarrec
f3829cf081
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
2020-02-20 16:16:36 +01:00
Florent Kermarrec
3a6f97fff3
build/sim: add Verilator FST tracing support.
2020-02-20 13:53:31 +01:00
enjoy-digital
8a715f3b12
Merge pull request #390 from gsomlo/gls-add-sdcard
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Import LiteSDCard support in to LiteX, using nexys4ddr as the initial test target
2020-02-20 08:17:54 +01:00
Gabriel Somlo
516cf40506
targets/nexys4ddr: add optional sdcard support
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Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
d4d2b7f7c6
bios: add litesdcard test routines to boot menu
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This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
7a2e33b817
targets/nexys4ddr: add ethernet via method instead of inheritance
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Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Florent Kermarrec
774a55a2aa
soc_core: fix missing init on main_ram
2020-02-19 14:59:58 +01:00
enjoy-digital
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets
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bios/boot: allow to customize flash offsets of Linux images
2020-02-18 17:54:13 +01:00
Florent Kermarrec
00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
Mateusz Holenko
659c244a0b
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 13:38:09 +01:00
Florent Kermarrec
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
Florent Kermarrec
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00