Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
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Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
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Florent Kermarrec
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2327710387
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liteeth/phy/gmii : set tx_er to 0 only if it exits
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2015-03-17 12:24:06 +01:00 |
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Florent Kermarrec
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408d0fd2dd
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liteeth: use default programmer in make.py
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2015-03-17 12:12:21 +01:00 |
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Florent Kermarrec
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ec6ae75065
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liteeth: use CRG from Migen in base example
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2015-03-17 12:11:51 +01:00 |
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Florent Kermarrec
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faf185d58d
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liteeth: make gmii phy generic
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2015-03-16 23:04:37 +01:00 |
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Florent Kermarrec
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c3c7f627d9
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liteeth/phy: typo (thanks sb)
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2015-03-12 21:54:10 +01:00 |
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Florent Kermarrec
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767d45727a
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uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
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2015-03-12 16:57:38 +01:00 |
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Florent Kermarrec
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b157031e8a
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uart/sim: add pty (optional, to use flterm)
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2015-03-09 23:29:06 +01:00 |
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Florent Kermarrec
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6cbf13036b
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liteeth/mac: fix padding limit (+1), netboot OK with sim platform
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2015-03-09 20:59:34 +01:00 |
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Florent Kermarrec
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47cceea222
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liteeth/mac: use Counter in sram and move some logic outside of fsms
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2015-03-09 20:22:14 +01:00 |
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Florent Kermarrec
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b10836a8eb
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liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
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2015-03-09 17:21:29 +01:00 |
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Florent Kermarrec
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360c849f21
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liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
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2015-03-09 13:23:39 +01:00 |
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Florent Kermarrec
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5dbd8af4be
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liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
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2015-03-09 13:23:37 +01:00 |
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Florent Kermarrec
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d20b9c2221
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uart: pass *args, **kwargs to sim phy
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2015-03-06 12:08:10 +01:00 |
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Florent Kermarrec
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af66ca7bad
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uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
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Florent Kermarrec
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95fa753149
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liteeth: add phy autodetect function (phy can still be instanciated directly)
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2015-03-06 10:10:34 +01:00 |
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Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
|
Florent Kermarrec
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200791c81d
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uart: generate ack for rx (serialboot OK with sim)
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2015-03-04 00:57:37 +01:00 |
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Florent Kermarrec
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7c058a52c9
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com/spi: use .format in tb
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2015-03-03 10:44:05 +01:00 |
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Florent Kermarrec
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1d4dc45436
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LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
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Florent Kermarrec
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b305b7828a
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sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
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2015-03-02 08:36:39 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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1e6d1deae8
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uart: add sim phy
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2015-03-01 16:52:50 +01:00 |
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Florent Kermarrec
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649cdeb265
|
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
|
bd4d3cd73b
|
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
|
liteXXX cores: remove Identifier duplication
|
2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
|
67ca0da1d9
|
liteXXX cores: share same methodology for on-board tests
|
2015-03-01 11:21:12 +01:00 |
|
Florent Kermarrec
|
b32a0e6f9e
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liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
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2015-02-28 23:33:00 +01:00 |
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Florent Kermarrec
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b34be816ec
|
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
|
litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
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912573f5c9
|
liteusb: move files and modify import to misoclib.com.liteusb
|
2015-02-28 11:18:00 +01:00 |
|
Florent Kermarrec
|
b647fe5823
|
merge liteusb
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2015-02-28 11:16:16 +01:00 |
|
Florent Kermarrec
|
2c3e8a2804
|
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
|
2015-02-28 11:04:48 +01:00 |
|
Florent Kermarrec
|
df0ba1b03c
|
litescope: create example_designs directory
|
2015-02-28 10:42:12 +01:00 |
|
Florent Kermarrec
|
c4ebf244a1
|
litescope: move files and modify import to misoclib.tools.litescope
|
2015-02-28 10:33:46 +01:00 |
|
Florent Kermarrec
|
a43c555ee3
|
misoclib/com: add spi (only SPIMaster for now)
|
2015-02-28 09:43:03 +01:00 |
|
Florent Kermarrec
|
2c51adcd68
|
misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |