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9081 Commits

Author SHA1 Message Date
Florent Kermarrec 5c43d4d091 litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 165a5b6760 soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000 2015-02-28 20:04:51 +01:00
Florent Kermarrec b53e2b0d6e fix xilinx/programmer with Vivado 2015-02-28 19:33:20 +01:00
Florent Kermarrec 6107b7844a test implementation on all targets and fix issues 2015-02-28 12:04:51 +01:00
Florent Kermarrec 1366ff5e26 move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
Florent Kermarrec 8564b7eb6a soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram) 2015-02-28 11:44:14 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 912573f5c9 liteusb: move files and modify import to misoclib.com.liteusb 2015-02-28 11:18:00 +01:00
Florent Kermarrec b647fe5823 merge liteusb 2015-02-28 11:16:16 +01:00
Florent Kermarrec 8e67d6e69f liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
Florent Kermarrec 2c3e8a2804 liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:04:48 +01:00
Florent Kermarrec 0dfca49e68 litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
Florent Kermarrec b6358be0a1 merge litesata 2015-02-28 10:48:08 +01:00
Florent Kermarrec df0ba1b03c litescope: create example_designs directory 2015-02-28 10:42:12 +01:00
Florent Kermarrec c4ebf244a1 litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
Florent Kermarrec b274e948dc merge litescope 2015-02-28 10:24:49 +01:00
Florent Kermarrec a43c555ee3 misoclib/com: add spi (only SPIMaster for now) 2015-02-28 09:43:03 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
Florent Kermarrec 87d8ff2de7 xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine) 2015-02-28 03:38:47 +01:00
Florent Kermarrec 6b93849a08 gensoc: parameter check is now more restrictive, add additional info to help user 2015-02-28 03:12:00 +01:00
Florent Kermarrec 8e04ef7b95 test minicon with de0nano (OK) and fix missing self in gensoc 2015-02-27 20:00:16 +01:00
Florent Kermarrec f1200d6388 gensoc: move I/O for rom initialization to make.py 2015-02-27 19:48:07 +01:00
Florent Kermarrec 074f576340 targets: add de0nano (100MHz, integrated bios and SDRAM) 2015-02-27 19:47:32 +01:00
Florent Kermarrec cb38580400 make.py fix indent 2015-02-27 18:58:36 +01:00
Florent Kermarrec 5e2e9338d2 bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash) 2015-02-27 17:22:44 +01:00
Florent Kermarrec b031c5edae targets: fix MiniSoC 2015-02-27 17:12:37 +01:00
Florent Kermarrec e07e124118 sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir 
We will maybe move things, but at least it's in MiSoC now
 2015-02-27 17:07:44 +01:00
Florent Kermarrec e82531cdf8 move dfi/lasmibus/wishbone2lasmi to MiSoC sdram 2015-02-27 16:54:22 +01:00
Florent Kermarrec 07b9cabd0d gensoc: make it more generic (a SoC does not necessarily have a CPU) 2015-02-27 16:39:00 +01:00
Florent Kermarrec 367db268ad reserve csr_map 0-->16 for gensoc internal csrs 2015-02-27 14:18:13 +01:00
Florent Kermarrec be0eb8d265 use cachesize reported in wishbone2lasmi 2015-02-27 14:13:38 +01:00
Florent Kermarrec 225a2d4704 report cachesize in wishbone2lasmi 2015-02-27 14:12:13 +01:00
Florent Kermarrec 9814001c79 create cpu dir and move lm32/mor1kx in it 2015-02-27 10:51:03 +01:00
Florent Kermarrec 9f636f7985 move memtest to sdram 2015-02-27 10:47:54 +01:00
Florent Kermarrec b817cf49b3 replace self._r_register by self._register in all CSR declaration 2015-02-27 10:36:09 +01:00
Florent Kermarrec e4de5a0c9d make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram) 2015-02-27 10:23:17 +01:00
Florent Kermarrec 77a6f580e2 gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts 2015-02-27 10:23:02 +01:00
Florent Kermarrec 617bc70d7f liteeth: move doc 2015-02-27 09:15:54 +01:00
Florent Kermarrec 54a8a52e90 xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...)) 2015-02-27 09:05:23 +01:00
Robert Jordens 2b0937153d xilinx/programmer: fix xc3sprog (GenericProgrammer) 2015-02-26 21:36:15 -07:00
Robert Jordens 2b12679ef6 add pipistrello target 2015-02-26 21:35:42 -07:00
Robert Jordens 8de5b947bd pipistrello: use fpgaprog 2015-02-26 21:34:02 -07:00
Robert Jordens ca52aa5b8c add fpgaprog programmer 2015-02-26 21:33:49 -07:00
Robert Jordens 5b5d2d15b8 add pipistrello platform 2015-02-26 21:33:42 -07:00
Sebastien Bourdeauducq ba26a400e3 Merge branch 'master' of https://github.com/m-labs/migen 2015-02-26 21:32:39 -07:00
Robert Jordens c9ed38dec8 gensoc: missing self. 2015-02-26 21:32:11 -07:00
Sebastien Bourdeauducq a3909bb5e2 Merge branch 'master' of https://github.com/m-labs/misoc 2015-02-26 21:28:12 -07:00
Sebastien Bourdeauducq 28c219ebd2 platforms/kc705: add user SMA clock 2015-02-26 16:22:22 -07:00