275932f56c
gen/fhdl/verilog: improve clock domain error reporting.
2020-11-10 13:27:29 +01:00
e52ffd2da0
gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.
2020-08-23 15:19:46 +02:00
fcc7058bfc
Fix DeprecationWarning for collections.abc
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DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
2020-08-22 13:39:30 +02:00
eeea30eada
litex/gen: remove io that has been replaced with litex/build/io (and should have been removed).
2020-07-07 08:14:42 +02:00
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
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When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
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This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
d92bd8ffaa
gen/fhdl/verilog: fix signed init values
2020-01-12 22:06:35 +01:00
94e239ff13
Add integer attributes
2019-12-19 09:03:12 +01:00
f8c5821658
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
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This reverts commit b845755995
2019-12-19 08:53:44 +01:00
b845755995
gen/fhdl/verilog: allow single element verilog inline attribute
2019-08-28 05:24:11 +02:00
daa4307d9e
add CONTRIBUTORS file and add copyright header to all files
2019-06-23 23:23:56 +02:00
68f12495cf
soc/integration: also add sha-1/date to generated software files
2019-04-23 13:17:54 +02:00
425741226c
build: add sha-1/date to generated verilog, change git_version to git_revision
2019-04-23 12:59:25 +02:00
99578bc68c
gen/sim/core: add args support on Display
2018-12-09 09:46:10 +01:00
fa260f5b42
gen/fhdl: add simulation Display, Finish support.
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In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
bf3b4eec34
gen: integrate migen changes
2018-12-04 21:06:51 +01:00
b796853893
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
6048a5291c
build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
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nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
2018-10-30 08:54:30 +01:00
c506c9752c
gen/fhdl/verilog: set direction to io signals
2018-10-29 11:41:04 +01:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
21bd26dcdd
Allow for multiple synthesis directives in specials.
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This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.
To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
2018-01-23 00:27:49 +00:00
ff0ad9a622
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
2017-12-29 19:56:52 -05:00
e42ab27f30
gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command
2017-09-13 13:47:25 +02:00
9509d9e361
gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers.
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read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
2017-07-24 13:39:08 +02:00
fe535db5ab
merge migen ee0e709 changes
2017-07-04 08:15:40 +02:00
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
bd876d4cd6
merge migen 9a6fdea3 changes
2017-06-28 22:47:13 +02:00
4ea7026747
gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
2017-06-10 21:53:53 +02:00
a36986a501
gen/fhdl/verilog: list available clock domains on keyerror
2017-06-05 14:33:46 +02:00
931ea5ac75
gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise
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latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
2017-06-01 19:00:22 +02:00
ff2a9c2176
gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned)
2017-05-31 13:23:31 +02:00
bb582619eb
gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer
2017-04-25 15:13:47 +02:00
0daeff8689
gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)
2017-04-25 10:56:19 +02:00
456cce3ec6
gen/genlib/cdc: import gcd from math and not fractions (deprecated)
2017-04-25 10:55:13 +02:00
4c7d460475
litex/gen/util/misc: import gcd from math and not fractions (deprecated)
2017-04-24 19:25:24 +02:00
f73eb5fe71
gen/genlib/misc: add BitSlip
2017-04-19 09:55:19 +02:00
b708b9cfba
gen/genlib/cdc: add gearbox
2017-04-19 09:54:51 +02:00
ff31959aea
merge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-13 03:55:00 +01:00
f0202db90f
gen/genlib/cdc: add GrayDecoder from misoc
2017-01-12 04:15:33 +01:00
677243bd8c
ElasticBuffer: infer reset
2016-10-14 09:43:09 +02:00
4362e5c528
gen/genlib/cdc: add ElasticBuffer
2016-10-13 17:04:39 +02:00
6a35337a09
gen/sim/vcd: allow continous update of vcd file and dynamic signals
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With continous update, VCD header needs to be writen at the beginning of the simulation.
When a new signal is created, we rewrite the header and the content.
2016-05-28 10:25:48 +02:00
65f74959b3
gen/sim/core: add Display support
2016-05-18 15:47:10 +02:00
6fe3e1237d
gen/fhdl/structure: fix Display
2016-05-18 12:41:29 +02:00
69f0035315
gen/fhdl: add Display for debug in simulation
2016-04-29 23:03:43 +02:00
42767286ca
gen/fhdl/verilog: add do in reserved_keywords
2016-04-27 17:43:25 +02:00
Florent Kermarrec
Xiretza
Arnaud Durand
Sergiusz Bazanski
William D. Jones
Robert Jordens