Dolu1990
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385a195d16
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few more var parameters
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2023-03-22 12:58:43 +01:00 |
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Dolu1990
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a755d839b3
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Add VexRiscvSmpClusterGen csrFull (wip)
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2023-03-22 11:07:18 +01:00 |
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Dolu1990
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5b47564024
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A few plugins config are now var
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2023-03-22 11:06:56 +01:00 |
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Dolu1990
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4972a27ae9
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More verbose main.cpp on failure, fix C.ADDSP regfile initialisation
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2023-03-22 11:06:23 +01:00 |
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Charles Papon
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0aa8cb11e0
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BranchPlugin do not use casez anymore
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2023-03-15 17:43:44 +08:00 |
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Charles Papon
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13061b8b2e
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debug unavailable is now BufferCC
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2023-03-15 09:50:09 +08:00 |
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Charles Papon
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876222d886
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Fix FPU access port instanciation when not needed
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2023-03-14 15:23:04 +08:00 |
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Charles Papon
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25eda80fee
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FpuTest document how to install berkley testfloat
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2023-03-10 14:46:21 +08:00 |
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Charles Papon
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94f19032f0
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FpuPlugin.access port added
Privileged debug access added
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2023-03-10 14:44:14 +08:00 |
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Charles Papon
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6be1531d36
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Fpu will not trap anymore on debug access if fs==0
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2023-03-10 09:17:01 +08:00 |
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Charles Papon
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1179c6551f
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Fix #321 #322 #333 FPU precision removal
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2023-03-08 16:00:22 +08:00 |
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Charles Papon
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f11c642cd6
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CfuPlugin encoding can now specify cmd/rsp less instruction
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2023-03-07 16:49:07 +08:00 |
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Charles Papon
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3cf8508db1
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DBus coupled timings improvement
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2023-03-05 20:31:40 +08:00 |
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Charles Papon
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153445ff21
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Fix CFU / FPU decoder stage fork on illegal instruction
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2023-03-05 20:29:53 +08:00 |
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Dolu1990
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cf70bc6b1f
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fix last push
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2023-03-03 14:20:12 +01:00 |
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Dolu1990
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b03b00a5c4
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Improve d$ coupled timings
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2023-03-03 14:13:51 +01:00 |
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Dolu1990
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5493c55ab0
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Alows Fetcher to have multiple debug injection ports
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2023-03-03 09:06:20 +01:00 |
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Dolu1990
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5f67075e30
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Fix FPU with F64 support, not removing mantissa precision from F32 #317
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2023-03-01 13:56:25 +01:00 |
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Dolu1990
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6f76a45e7d
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update mmu test
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2023-02-23 15:54:39 +01:00 |
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Dolu1990
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d7e9c726c3
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Fix datacache initial flush
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2023-02-23 14:42:21 +01:00 |
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Dolu1990
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c5689e512c
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CsrPlugin now provide regression args
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2023-02-23 12:00:25 +01:00 |
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Dolu1990
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a40d5f19b2
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Fix MMU A and D flag handeling
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2023-02-23 12:00:08 +01:00 |
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Dolu1990
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344b2d4eda
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TestIndividual supervisor missing CSR=yes
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2023-02-23 11:59:13 +01:00 |
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Dolu1990
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9605b663bf
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D$ now support thightly coupled ram.
Add IBusDBusCachedTightlyCoupledRam plugin
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2023-02-22 15:26:14 +01:00 |
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Dolu1990
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220b599c9a
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Fix d$ invalidation when the mmu is enabled
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2023-02-22 13:16:02 +01:00 |
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Dolu1990
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15a665af53
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fix too early
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2023-02-19 09:51:18 +01:00 |
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Dolu1990
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d078297496
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fix too early
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2023-02-19 09:48:59 +01:00 |
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Dolu1990
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a780eec616
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Merge branch 'debug-debug' into dev
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2023-02-13 10:04:41 +01:00 |
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Dolu1990
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33e820bdf9
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FPU now implement a less pessismitic dirty logic
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2023-02-08 15:16:53 +01:00 |
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Dolu1990
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3ae51cdeb8
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Fix fpu csr access on fs===0 now also trap
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2023-02-08 14:44:04 +01:00 |
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Dolu1990
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692f604dd5
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Fix VexRiscvSmpClusterGen without linux debug minimal features
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2023-02-08 11:28:21 +01:00 |
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Dolu1990
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cbc89093b3
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fpu csr access on fs===0 now also trap
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2023-02-07 10:18:08 +01:00 |
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Dolu1990
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9acc5ddc1c
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Fix FPU access trap on fs = 0 #297
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2023-02-06 11:44:44 +01:00 |
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Dolu1990
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fc9a9d25ed
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sync
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2023-02-06 11:43:49 +01:00 |
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Dolu1990
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2bc6e70f03
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Fix RVC decompressor don't care #296
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2023-01-18 15:19:33 +01:00 |
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Dolu1990
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7d3a862183
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Fix Litex cluster scopt update
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2023-01-16 18:10:51 +01:00 |
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Dolu1990
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aea2e90d1e
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Upgrade to SBT 1.6.0
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2023-01-16 17:58:23 +01:00 |
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Dolu1990
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773f268f37
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Fix FPU test syntax
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2022-12-01 12:04:16 +01:00 |
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Dolu1990
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fb084327da
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Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert
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2022-11-28 16:30:47 +01:00 |
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Dolu1990
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eafeb5fe49
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Add EmbeddedRiscvJtag.debugCd
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2022-11-28 11:04:02 +01:00 |
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Dolu1990
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a25ae96d33
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comment debug code
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2022-11-21 14:02:35 +01:00 |
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Dolu1990
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572ca3fcfa
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Privileged debug fake maskmax to 31
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2022-11-21 14:01:28 +01:00 |
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Dolu1990
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5a8cdee884
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Fix CsrPlugin dcsr.stepie
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2022-11-21 11:55:07 +01:00 |
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Dolu1990
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4ae7386904
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Merge pull request #276 from LYWalker/master
Add ability to debug over Intel Virtual JTAG
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2022-11-18 17:38:50 +01:00 |
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Dolu1990
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e19e59b55c
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Clear mprv on xretAwayFromMachine
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2022-11-17 15:03:47 +01:00 |
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Dolu1990
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663174bc73
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Privileged debug now implement stoptime stopcount
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2022-11-17 13:58:29 +01:00 |
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Dolu1990
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36c3346e51
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ensure rvc 0 is detected as a illegal instruction
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2022-11-17 11:03:45 +01:00 |
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Dolu1990
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5e17ab62d6
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Fix RISC-V debug hardware breakpoints
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2022-11-14 14:45:11 +01:00 |
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Dolu1990
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fe68b8494e
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Fix a few RISC-V official debug support :
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
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2022-11-11 14:05:38 +01:00 |
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Dolu1990
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2504f9b9b9
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RISC-V debug havereset implemented
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2022-11-10 15:49:07 +01:00 |