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VexRiscv
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476 Commits

Author SHA1 Message Date
Dolu1990 e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990 2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990 af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990 ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990 7cbe399f1f Fix some supervisor CSR access 2019-03-20 23:25:52 +01:00
Dolu1990 6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990 39b2803914 Fix some CsrPlugin flags issues 2019-03-20 20:27:47 +01:00
Dolu1990 6c2fe934fd Bring changes and fixies from @kgugala @daveshah1. Thanks guys ! 2019-03-20 16:27:35 +01:00
Dolu1990 130a69eeae Pass regressions machinemode with CSR config including Supervisor 2019-03-20 14:14:59 +01:00
Dolu1990 d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990 3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990 ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990 3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990 ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990 8f22365959 Disable MMU in machine mode 2019-03-19 22:21:30 +01:00
Dolu1990 3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990 915db9d6c9 cleaning 2019-03-18 20:50:19 +01:00
Dolu1990 001ca45c57 Add cachless dBus IBus access right checks 2019-03-18 12:52:22 +01:00
Dolu1990 c490838202 Added MMU support into cacheless DBus IBus plugins (for testing purposes) 
Probably full of bugs, need testing
 2019-03-18 12:17:43 +01:00
Dolu1990 ffa489d211 hardware refilled MmuPlugin wip 2019-03-17 21:06:47 +01:00
Dolu1990 bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990 434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990 e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990 11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990 927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990 dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990 d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990 76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990 d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990 281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990 1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990 f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990 9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990 52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990 68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990 eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990 ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990 3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00
Dolu1990 58d7a4784d move HexTools into SpinalHDL lib 2018-11-30 17:39:33 +01:00
Dolu1990 b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus 
Move PipelinedMemoryBus into SpinalHDL lib
 2018-11-30 17:37:17 +01:00
Dolu1990 2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990 7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990 c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990 0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990 75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990 cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990 0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990 fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990 b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990 b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990 662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990 978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00
Dolu1990 c8ac214097 Optimize CSR 2018-10-28 02:18:27 +02:00
Dolu1990 51de2b5820 SimpleBusInterconnect now adapte address width 2018-10-28 02:18:08 +02:00
Dolu1990 00bf84b7f8 Add SimpleBusInterconnect 2018-10-25 23:47:05 +02:00
Dolu1990 4ed4af6a3e SrcPlugin add decodeAddSub option 2018-10-24 01:28:37 +02:00
Dolu1990 372063582c Improve CsrPlugin CombinatorialPaths 2018-10-23 19:07:08 +02:00
Dolu1990 7096c63d50 Add more SimpleBus utilies 2018-10-23 17:46:31 +02:00
Dolu1990 7c0f2dc713 Add SimpleBus object 2018-10-20 12:39:30 +02:00
Morard Dany 85e696b286 CsrPlugin : Add mtvecModeGen 2018-10-16 14:53:41 +02:00
Dolu1990 905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00
Dolu1990 f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990 2b29690010 Clean branch plugin lsb bit calculation 
BranchPlugin doesn't try anymore to catch exception when RVC is on
 2018-10-12 12:24:52 +02:00
Dolu1990 eea92154ae fetcher force PC LSB to be zero 2018-10-12 12:02:52 +02:00
Dolu1990 0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990 8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990 c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990 40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990 68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990 0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990 c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990 0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990 65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990 7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990 39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990 5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990 37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990 9a3510f63d Map all supervisor registers 2018-09-27 19:03:57 +02:00
Dolu1990 acd1ca422a wip 2018-09-27 18:24:40 +02:00
Dolu1990 6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL 2018-09-27 00:55:30 +02:00
Dolu1990 aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990 1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990 86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990 56fd73fbbc Add missing bin files 2018-09-23 19:26:11 +02:00
Dolu1990 bdc3246f5a Fix xip gitignore 2018-09-23 19:23:43 +02:00
Dolu1990 5024cc5616 Hardware breakpoint feature added 
Murax XIP debugging passed tests
 2018-09-20 13:11:20 +02:00
Dolu1990 ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990 b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990 3e17461cc7 Add optional XIP to Murax 2018-09-16 11:00:56 +02:00
Dolu1990 d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990 791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990 0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Dolu1990 7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990 38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00