0648c04158
Updated comment, added link to clocking documentation.
2020-05-25 14:48:24 -07:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
...
Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
0d549a8c89
platforms: add forest_kitten_33 initial platform suppport.
2020-05-24 11:22:02 +02:00
12b54a7a7f
platforms/alveo_u250: add clk300 clock constraints.
2020-05-24 11:18:30 +02:00
46f78b5002
nexys_video: add usb_fifo pins.
2020-05-22 14:28:55 +02:00
445338e2e7
platforms/nexys_video: add specific openocd cfg (use channel 1).
2020-05-22 14:12:45 +02:00
76551dec4c
platforms/nexys_video: add sdcard pins, move clk/rst to top.
2020-05-20 13:05:18 +02:00
83457b8791
platforms/arty: add _sdcard_pmod_io.
2020-05-20 12:09:43 +02:00
587caf7584
paltforms/marblemini: add break_off_pmod.
2020-05-19 15:42:53 +02:00
c2cd863658
platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash.
...
The Platform file should not contain import code related to cores, this has to be done in the target.
2020-05-19 15:29:25 +02:00
3f0f12011b
Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params
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ECP5-EVN SpiFlash parameters
2020-05-19 15:16:25 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
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[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
4faa91c7f2
platforms/marblemini: review/cleanup.
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- add copyrights.
- add link to documentation.
- reindent code.
- rename some IOs (for consistency with the others platforms).
- add pullup on clk20_vcxo_en.
- set clk20_vcxo as default clock.
- remove ununnecessary eth constraints. (we are using IO primitives).
- move PMODS to connectors (for consistency with others platforms).
2020-05-09 10:16:42 +02:00
4ffdcb5ea9
Merge pull request #75 from jersey99/marblemini
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Marblemini [https://github.com/berkeleylab/marble-mini/ ]
2020-05-09 09:39:40 +02:00
e4ccfcfad1
platforms/marblemini.py: Cleanup. Add openocd for programming marblemini
2020-05-08 17:20:14 -07:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
a7d6de78ae
Merge branch 'master' into marblemini
2020-05-07 12:19:47 -07:00
99c04358bf
platforms/pano_logic_g2: simplify/cleanup.
2020-05-07 16:35:34 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
86648ec7d8
platforms/vcu118: rename ddram_second_channel to ddram:1.
2020-05-05 09:54:11 +02:00
e1820c7831
platforms/ac701: indent HPC.
2020-05-05 09:49:59 +02:00
2129b67779
platforms: make sure all plarforms have separators.
2020-05-05 09:47:55 +02:00
ea0eda9f75
platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series.
2020-05-05 09:42:34 +02:00
088cceca8b
Add Alveo U250 platform and target
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
0ba8045789
Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H
2020-04-28 21:56:33 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4ad6042e07
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:36:18 +02:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
4d7135f167
platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD).
2020-04-09 23:06:57 +02:00
2cf3c3e845
platforms: cosmetic cleanups.
2020-04-09 23:05:13 +02:00
df5de8816d
platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM.
2020-04-09 18:53:06 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
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ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
9ae8a0cc11
colorlight_5a_75b/v7.0: add spiflash pins.
2020-03-31 16:18:12 +02:00
a43072ac40
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-03-28 13:08:46 +01:00
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
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programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
8afc9a5b03
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 11:27:34 +01:00
89dd00d3a2
platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).
2020-03-27 13:01:36 +01:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
6e6b6dac55
platforms/orangecrab: add spisdcard pins.
2020-03-25 10:21:57 +01:00
87fd4dc059
platforms/minispartan6: add spisdcard pins.
2020-03-25 09:53:04 +01:00
92f793f9c5
platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 19:58:12 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard
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Move trellisboard target to SoCCore, add SPI-mode SDCard support
2020-03-20 19:07:00 +01:00
fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
396b0383c8
platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads
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Add support for SPI-mode SDCard interface. Also, add pull-up and
slew constraints to the standard sdcard interface.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
d0d047dfa4
platforms/ulx3s: add spisdcard pins.
2020-03-19 15:14:05 +01:00
6ab13a0661
de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
2020-03-19 11:09:48 +01:00
db9d5489ec
Merge pull request #56 from rob-ng15/master
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de10nano add in support for MiSTer secondary sd card
2020-03-19 11:07:40 +01:00
57bcadb5b4
platforms/nexys4ddr: add spisdcard pins.
2020-03-19 11:04:11 +01:00
f3d7f5880f
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:09:52 +01:00
a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging
2020-03-18 12:11:57 +00:00
ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5
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platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:30:12 +01:00
90de99eb46
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:03:31 +01:00
75286f8a9b
platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)
2020-03-10 14:57:39 +01:00
95e1a05bf1
platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:29:49 +01:00
3f191c8561
mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4).
2020-03-09 09:28:25 +01:00
f4ae21a7a2
zcu104: fix copyrights.
2020-03-09 09:24:06 +01:00
5031c11d57
mercury_xu5: add missing copyrights.
2020-03-09 09:23:08 +01:00
8c535d15f2
platforms/mercury_xu5: replace ' with ".
2020-03-09 09:21:27 +01:00
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5
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add Enclustra Mercury XU5 board
2020-03-09 09:11:15 +01:00
d002059e0b
add Enclustra Mercury XU5 board
2020-03-05 10:52:32 +01:00
ce9b67e2ee
Added icebreaker platform and target.
...
Target is heavily based on Fomu.
2020-03-05 00:12:18 -08:00
7b4ca20ff4
platforms.colorlight_5a_75b: add J1-J8 connectors
2020-02-28 06:09:44 -08:00
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +01:00
aaa10c69eb
platforms/colorlight_5a_75b: add default_clk_name/period
2020-02-27 11:16:49 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
18f65a7f9d
platforms/kc705: cleanup ddram.
2020-02-27 11:06:35 +01:00
d4460c11a5
platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
2020-02-27 10:43:41 +01:00
58f588f69e
platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings
2020-02-27 10:43:01 +01:00
d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
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Ease switching between ddram_32 and ddram_64.
2020-02-27 10:05:17 +01:00
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +01:00
22b0449509
Merge pull request #47 from antmicro/zcu104
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Add support for ZCU104 board
2020-02-27 09:51:54 +01:00
608541d5b8
add ZCU104 board
2020-02-26 13:53:21 +01:00
e516ff3452
vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:51 +01:00
9d2ca50c5f
kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:35 +01:00
83d2c71099
platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
2020-02-25 18:32:42 +01:00
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +01:00
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +01:00
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +01:00
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -05:00
2cf4e084ec
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-23 10:01:41 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Skip Hansen
Florent Kermarrec
Vamsi K Vytla
David Shah
Ilya Epifanov
Dave Marples
Staf Verhaegen
David Sawatzke
Piotr Binkowski
Greg Davill
Gabriel Somlo
rob-ng15
Jędrzej Boczar
Piotr Esden-Tempski
Tom Keddie
Fei Gao
Gwenhael Goavec-Merou