f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
6335717eca
targets/orangecrab.py: propagate command arguments
...
The parsed args are stripped off by soc_core_argdict() (called from
soc_sdram_argdict() so we have to pass them explicitly (or pass the
original "args", but this mimics the rest of the code in the repo).
This fixes #72
2020-05-06 18:24:11 -07:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
117d1a1c75
prog: add colorlight_5a_75b openocd config.
2020-05-06 16:01:59 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
86648ec7d8
platforms/vcu118: rename ddram_second_channel to ddram:1.
2020-05-05 09:54:11 +02:00
e1820c7831
platforms/ac701: indent HPC.
2020-05-05 09:49:59 +02:00
2129b67779
platforms: make sure all plarforms have separators.
2020-05-05 09:47:55 +02:00
ea0eda9f75
platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series.
2020-05-05 09:42:34 +02:00
588bbac719
add prog directory with some Xilinx OpenOCD configurations files.
2020-05-05 09:11:06 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
...
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
088cceca8b
Add Alveo U250 platform and target
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
0ba8045789
Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H
2020-04-28 21:56:33 +02:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4ad6042e07
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:36:18 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
...
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
4d7135f167
platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD).
2020-04-09 23:06:57 +02:00
2cf3c3e845
platforms: cosmetic cleanups.
2020-04-09 23:05:13 +02:00
df5de8816d
platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM.
2020-04-09 18:53:06 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
...
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
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ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
5f629c203b
targets/vcu118: fix clk500 typo.
2020-04-07 13:53:22 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
19e5366ad1
targets/colorlight_5a_75b: update sys/sys_ps phases.
2020-03-31 18:18:45 +02:00
9ae8a0cc11
colorlight_5a_75b/v7.0: add spiflash pins.
2020-03-31 16:18:12 +02:00
a43072ac40
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-03-28 13:08:46 +01:00
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
...
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
8afc9a5b03
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 11:27:34 +01:00
89dd00d3a2
platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).
2020-03-27 13:01:36 +01:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
555bf6c4dc
targets/Ultrascale(+): enable USDDRPHY_DEBUG.
2020-03-26 09:17:09 +01:00
4053c02d7e
targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.
2020-03-25 19:38:36 +01:00
85f38876c2
targets: update PCIe on Numato targets.
...
Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
6e6b6dac55
platforms/orangecrab: add spisdcard pins.
2020-03-25 10:21:57 +01:00
87fd4dc059
platforms/minispartan6: add spisdcard pins.
2020-03-25 09:53:04 +01:00
24033e331c
targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 19:59:42 +01:00
92f793f9c5
platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 19:58:12 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
bf3c9dc9bf
orangecrab: Add sdram selection option
2020-03-22 20:41:12 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
78224b1e56
targets/colorlight_5a_75b: add SDRAM.
2020-03-21 22:11:47 +01:00
a95a4eed3f
targets/colorlight_5a_75b: switch to add_ethernet/add_etherbone methods.
2020-03-21 21:50:05 +01:00
7bba5caab0
targets/c10prefkit: remove keep attributes (no longer needed, added automatically).
2020-03-21 21:44:44 +01:00
6c31933e89
targets: switch to add_etherbone method.
2020-03-21 21:40:45 +01:00
159386e3d3
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 20:00:56 +01:00
3fb3ba18e8
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-21 18:29:52 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard
...
Move trellisboard target to SoCCore, add SPI-mode SDCard support
2020-03-20 19:07:00 +01:00
fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
f021c1de5f
targets/trellisboard: add '--with-spi-sdcard' build option
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-20 07:14:13 -04:00
69a78c8c66
targets/trellisboard: switch to SoCCore, use add_ethernet() method
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
396b0383c8
platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads
...
Add support for SPI-mode SDCard interface. Also, add pull-up and
slew constraints to the standard sdcard interface.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
d0d047dfa4
platforms/ulx3s: add spisdcard pins.
2020-03-19 15:14:05 +01:00
6ab13a0661
de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
2020-03-19 11:09:48 +01:00
db9d5489ec
Merge pull request #56 from rob-ng15/master
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de10nano add in support for MiSTer secondary sd card
2020-03-19 11:07:40 +01:00
57bcadb5b4
platforms/nexys4ddr: add spisdcard pins.
2020-03-19 11:04:11 +01:00
f3d7f5880f
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:09:52 +01:00
bc6ef0bc48
Allow access to secondary sd card via hardware spi bitbanging
2020-03-18 12:13:37 +00:00
a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging
2020-03-18 12:11:57 +00:00
a99d258411
targets/icebreaker: use simplified version closer to the others targets.
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Add description of the board, link to the crowdsupply campaign and to the more complete example.
2020-03-13 09:43:43 +01:00
74a5ffb9ef
targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
...
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
2020-03-10 16:58:30 +01:00
e2a66090ee
targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
2020-03-10 16:55:22 +01:00
cf58550bba
targets/Ultrascale+: use USPDDRPHY.
2020-03-10 16:06:48 +01:00
ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5
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platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:30:12 +01:00
90de99eb46
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:03:31 +01:00
75286f8a9b
platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)
2020-03-10 14:57:39 +01:00
95e1a05bf1
platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:29:49 +01:00
Florent Kermarrec
Tommy Thorn
David Shah
Ilya Epifanov
Dave Marples
Staf Verhaegen
David Sawatzke
Piotr Binkowski
Greg Davill
Gabriel Somlo
rob-ng15
Jędrzej Boczar