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1396 commits

Author SHA1 Message Date
Hans Baier
53e9e0914e qmtech_ep4cgx150 80MHz default works well 2022-04-16 15:00:01 +07:00
Hans Baier
b41d72e1d0 add board support for QMTech EP4CGX150 2022-04-16 06:36:24 +07:00
Florent Kermarrec
23b1b15486 Add initial/minimal Pluto SDR support. 2022-04-14 12:13:03 +02:00
Alex Petrov
1e00a43fdd board u420t kintex update v0.2 2022-04-13 00:12:59 +03:00
Alex Petrov
89570b005c Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board 2022-04-12 22:38:14 +03:00
Florent Kermarrec
b99d788732 fairwaves/xtrx: Update with xtrx_julia improvements. 2022-04-12 17:42:52 +02:00
Florent Kermarrec
dd27a3473b platforms: Add LambdaConcept's PCIe Screamer/M2. 2022-04-01 11:41:07 +02:00
Florent Kermarrec
00ff61baa9 targets: Simplify clock domains and remove useless reset_less. 
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
 2022-04-01 11:30:38 +02:00
Florent Kermarrec
867489d855 xilinx_zcu106: Add PCIe Gen3 X4 support. 2022-04-01 10:01:06 +02:00
Franck Jullien
299d4d66d6 efinix: ti60f225 add MIPI RX 2022-03-29 15:29:59 +02:00
enjoy-digital
13e5062793
Merge pull request #379 from chmousset/add_t8_devkit 
[enh] added efinix t8f81 dev kit
 2022-03-28 14:58:21 +02:00
enjoy-digital
e6a9f44580
Merge pull request #378 from antmicro/add-missing-peripherals 
DDR4 datacenter: add missing peripherals
 2022-03-28 14:40:22 +02:00
enjoy-digital
83d7c3fb39
Merge pull request #377 from Johnsel/arduino_mkrvidor4000 
Board support for Arduino MKR Vidor 4000
 2022-03-28 14:34:59 +02:00
Charles-Henri Mousset
7a68dcc79b [enh] added efinix t8f81 dev kit 2022-03-26 09:52:20 +01:00
Alessandro Comodi
33516a40f4 antmicro_datacenter: add missing peripherals 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-25 13:49:41 +01:00
Alessandro Comodi
77cb866233 antmicro_datacenter: add HDMI output 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-25 10:03:07 +01:00
John Simons
501c50ff79 Fixed serial port comments hinting the correct pins. 2022-03-24 08:04:47 -07:00
John Simons
901942bda6 Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================-- 
CPU:BUS:E 32-bit @ 4GiB
CSR:16-bit @ 48MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 21.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
 2022-03-24 07:39:14 -07:00
Hans Baier
e445c9ec71 qmtech_5cefa2: make serial pins consistent with other boards 2022-03-24 18:52:28 +07:00
Florent Kermarrec
c081177d77 pynq_z1/zybo_z7: Update .xci (With changes from #99). 2022-03-24 09:15:36 +01:00
Sylvain Munaut
bcedf573e0 adi_adrv2crr: Add IO definition for the AD9545 reset line 
We use PULLUP on it so that the AD9545 is by default held out
of reset without the user having to do anything ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut
cdb78efd3c adi_adrv2crr: Document I2C devices attached 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut
6c31f16df2 adi_adrv2crr: Fix I2C signal assignement 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Florent Kermarrec
bb974ae1af decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support. 2022-03-23 15:24:49 +01:00
Florent Kermarrec
73458ae9d7 decklink_quad_hdmi_recorder: Add Serial/UART pins. 2022-03-23 11:08:51 +01:00
enjoy-digital
d399f33dda
Merge pull request #374 from smunaut/adrv2crr 
adi_adrv2crr: Upgrade part to speedgrade 2
 2022-03-23 09:09:57 +01:00
enjoy-digital
4ca527974b
Merge pull request #373 from goran-mahovlic/patch-1 
faster sdcard boot on 2.0
 2022-03-23 08:07:49 +01:00
Sylvain Munaut
dc92584681 adi_adrv2crr: Upgrade part to speedgrade 2 
Even though the schematic and bom call for speedgrade 1, this was only for
the prototypes.

All productions units have been updated to speedgrade 2.

See this thread:
https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade

And the official HDL project for the board:
https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-22 23:36:41 +01:00
Florent Kermarrec
ce4b627e3c targets: Remove l2_size workaround (no longer required). 2022-03-22 19:13:23 +01:00
Goran Mahovlic
68c23e9251
faster sdcard boot on 2.0 2022-03-22 17:54:12 +01:00
Florent Kermarrec
2a206def0f targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less). 2022-03-22 17:32:35 +01:00
Matt Johnston
53c221a1fa butterstick: set ethernet rx_delay to 0ns 
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.

In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
 2022-03-22 13:51:03 +08:00
John Simons
b8b0aead28 Added basic support for Arduino MKR Vidor 4000 2022-03-21 18:54:29 -07:00
Florent Kermarrec
9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec
d90e260414 targets/digilent_atlys: Fix target. 2022-03-21 17:38:02 +01:00
Florent Kermarrec
cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec
eb8657f515 gsd_orangecrab: Revert dm_remapping (Useful when built with VexRiscv-SMP and native LiteDRAM interface). 2022-03-18 12:56:13 +01:00
Florent Kermarrec
3ebad7f7cc gsd_orangecrab/butterstick: Add assert on devices. 2022-03-18 10:44:21 +01:00
Florent Kermarrec
9faa805ab9 alinx_ax7010: Review/Cleanup. 2022-03-17 11:31:02 +01:00
enjoy-digital
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010 
Add ALINX AX7010 board support
 2022-03-17 09:52:04 +01:00
Florent Kermarrec
0f82db26da rcs_artic_term_bmc_card: Fix is -> ==. 2022-03-17 09:45:47 +01:00
Florent Kermarrec
496b2cfab9 targets/gowin: Switch to get_bitstream_filename. 2022-03-17 09:40:10 +01:00
Florent Kermarrec
773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Yonggang Liu
94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py 2022-03-17 11:24:24 +08:00
Yonggang Liu
0e7145b4a1
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py 2022-03-17 11:21:42 +08:00
Florent Kermarrec
0745162a29 xilinx_zcu102: Review/Cleanup for consistency with others boards. 
Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
 2022-03-16 18:47:05 +01:00
Joseph Faye
adbcc2e547
add zcu102 target file 2022-03-16 15:55:37 +01:00
Joseph Faye
f4a48e51d7
add xilinx_zcu102 platform 2022-03-16 15:37:02 +01:00
Yonggang Liu
9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py 2022-03-15 15:51:13 +08:00
Yonggang Liu
5365c7fce4
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py 2022-03-15 15:50:09 +08:00
enjoy-digital
a962d8249f
Merge pull request #366 from gsomlo/gls-nexys-video-sata-pll 
targets/nexys-video: Add support for sata pll refclk
 2022-03-13 12:30:58 +01:00
Yonggang Liu
9c55773275
Add files via upload 
Add zynq_xc7z010 board support
 2022-03-12 12:33:41 +08:00
Yonggang Liu
4159faf48b
Add files via upload 
Adding zynq_xc7z010 board support
 2022-03-12 12:20:54 +08:00
Gabriel Somlo
9f9afeaafa targets/nexys-video: Add support for sata pll refclk 2022-03-11 14:40:21 -05:00
Robert Szczepanski
688377de7c lpddr4_test_board: Fix button pin 2022-03-11 15:59:43 +01:00
enjoy-digital
3b74673a93
Merge pull request #363 from curliph/master 
add Gowin programmer support
 2022-03-08 17:26:50 +01:00
Florent Kermarrec
f52a915487 lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer). 
I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5.

Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar  8 2022 15:34:22
 BIOS CRC passed (c7fe9ecd)

 Migen git sha1: ac70301
 LiteX git sha1: 7ebc7625

--=============== SoC ==================--
CPU:		FireV-STANDARD @ 75MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |01110000| delays: 02+-01
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: 02+-01
  m1, b00: |01110000| delays: 02+-01
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 23.4MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
 2022-03-08 15:40:52 +01:00
Florent Kermarrec
39e4e211bb targets/decklink_mini_4k: Add build/use instructions. 2022-03-08 14:14:18 +01:00
curliph
2df7fd573c
Update sipeed_tang_nano_9k.py 
Add Gowin programmer support
 2022-03-08 14:04:28 +08:00
curliph
6eb906a2ca
Update sipeed_tang_nano_9k.py 
add Gowin programmer support
 2022-03-08 14:00:53 +08:00
curliph
4c9bc53a3c add Win/powershell and WSL support 2022-03-08 13:24:56 +08:00
Florent Kermarrec
cadfde4d39 litex_acorn_baseboard: Add SerDes refclk and m2_tx/rx pins. 2022-03-07 18:41:53 +01:00
enjoy-digital
50cc75fd56
Merge pull request #361 from smunaut/adrv2crr 
adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
 2022-03-07 09:24:36 +01:00
Florent Kermarrec
37783ff9fd colorlight_5a_75e: Fix _connectors_v6_0/j16 first pin (thanks @WhichWayWazzit). 2022-03-07 09:16:07 +01:00
Sylvain Munaut
ec28ca8fa3 adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM 
This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.

Note that the PCIe support requires :
 - Change the .xci in the litepcie to use the right Quad
 - Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
   timing constrainst of litepcie apply correctly

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-03 22:17:09 +01:00
Florent Kermarrec
0f2e13fdf7 sqrl_fk33: Add HBM2 support (from https://github.com/enjoy-digital/fk33_hbm2_test). 2022-03-03 17:34:48 +01:00
Florent Kermarrec
99a66274c8 xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX. 2022-03-03 16:11:48 +01:00
Florent Kermarrec
b80c7a7843 targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required. 2022-03-03 15:50:53 +01:00
Alessandro Comodi
7933e9462e antmicro_datacenter: fix i2c pads assignment 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-01 16:35:15 +01:00
Florent Kermarrec
7a5fe4c221 efinix_titanium_ti60_f225_dev_kit: Update iobank_info with the values used in the video example design. 2022-03-01 14:01:43 +01:00
Florent Kermarrec
2450d8db4f tools: Remove extract_xdc_pins, has only been useful for Alveo boards and could be integrated in a Gist. 2022-03-01 14:00:42 +01:00
Alessandro Comodi
db2d83ea29 antmicro_datacenter: use 100 MHz and add i2c master 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-01 13:00:36 +01:00
Piotr Binkowski
0b80890119 antmicro_datacenter: add 1 cycle of latency for RCD IC 2022-03-01 12:43:08 +01:00
Piotr Binkowski
d6fddc746f antmicro_datacenter: use single rank configuration 2022-03-01 12:43:08 +01:00
Piotr Binkowski
9976b47f72 antmicro_datacenter: generate outputs for rowhammer-tester 2022-03-01 12:43:08 +01:00
Piotr Binkowski
37905d1f34 antmicro_datacenter: use correct DQS pins 2022-03-01 12:43:08 +01:00
Karol Gugala
5359fc5bfc antmicro_datacenter: use A7DDRPHY 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2022-03-01 12:43:08 +01:00
Karol Gugala
73b5143cec antmicro_datacenter: add DCI_CASCADE 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2022-03-01 12:43:08 +01:00
Florent Kermarrec
2c4d31066f digilent_arty_z7: Defaults to no_uart. 2022-03-01 11:15:30 +01:00
Florent Kermarrec
0ceb15938f digilent_arty_z7: Remove fake serial. 2022-03-01 11:05:59 +01:00
Florent Kermarrec
673676e3cb digilent_arty_a7: Switch to VivadoProgrammer. 2022-03-01 10:48:22 +01:00
Florent Kermarrec
e16e5e0591 digilent_arty_z7: Fix add_period_constraint. 2022-03-01 10:30:14 +01:00
enjoy-digital
1320f3bd23
Merge pull request #357 from DaveBerkeley/colorlight_i9 
Add ColorLight i9 v7.2
 2022-03-01 10:07:55 +01:00
Florent Kermarrec
a19c03fa55 targets: Switch to generic/portable HyperRAM core from LiteX. 2022-03-01 09:10:19 +01:00
Dave Berkeley
c9d009c735 Add ColorLight i9 v7.2 2022-02-28 14:08:49 +00:00
enjoy-digital
11dfe225fa
Merge pull request #356 from fjullien/add_mipi_tx 
efinix: add MIPI TX to platform Ti60
 2022-02-25 16:53:11 +01:00
Franck Jullien
c54e92c47d efinix: add MIPI TX to platform Ti60 2022-02-25 15:15:14 +01:00
inc
2311db18f8 add initial support for kröte fpga board 2022-02-25 14:22:19 +01:00
Florent Kermarrec
1623ba5942 targets/stlv7325: Reduce sys_clk_freq to 100MHz. 
See https://github.com/enjoy-digital/litedram/issues/285.
 2022-02-25 09:04:07 +01:00
Florent Kermarrec
872113e1cc stlv7325: Add SDCard support. 2022-02-24 18:02:43 +01:00
Florent Kermarrec
a08f346d90 stlv7325: Add Etherbone support (untested). 2022-02-24 17:43:53 +01:00
Florent Kermarrec
b1550f006a stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer. 2022-02-24 17:17:08 +01:00
Andrew Gillham
174d958ca7 Initial support for STLV7325 Kintex-7 board. 2022-02-23 18:28:55 +01:00
enjoy-digital
6661947d96
Merge pull request #354 from madscientist159/master 
Add initial support for RCS Arctic Tern boards
 2022-02-23 18:06:08 +01:00
Florent Kermarrec
1717af68ac targets/sqrl_acorn/ddr3: Disable write_latency_calibration. 
Introduce some memtest failures on some boards.
 2022-02-23 10:38:43 +01:00
Raptor Engineering Development Team
ae4b3c0938 Add initial support for RCS Arctic Tern boards 2022-02-21 20:04:51 -06:00
Ilia Sergachev
85397818d9 add Xilinx ZCU216 support 2022-02-21 19:14:13 +01:00
Florent Kermarrec
7d84e6e863 efinix_titanium_ti60_t225: Add SPI/Native SDCard support. 
Both modes working with 8559b88ad8.
 2022-02-21 10:35:06 +01:00
Florent Kermarrec
df36cdbcc9 siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax). 2022-02-18 11:47:08 +01:00
Florent Kermarrec
d85f88f42a siglent_sds1104xe: Reduce DRAM's width to 16-bit for now (to use NaxRiscv). 2022-02-16 17:59:40 +01:00
Florent Kermarrec
08a79fa3ac lattice_ecp5_vip: Minor cleanups, fix CI. 2022-02-15 10:58:38 +01:00
enjoy-digital
30afe26669
Merge pull request #348 from hubmartin/ecp5-vip 
Draft: Add Lattice ECP5 VIP board + HDMI output board support
 2022-02-15 08:53:57 +01:00
enjoy-digital
896884dd21
Merge branch 'master' into axu2cga_software 2022-02-15 08:21:29 +01:00
enjoy-digital
6bbf8c8268
Merge pull request #351 from sergachev/litex_baseboard_openocd 
add openocd config for litex acorn baseboard
 2022-02-15 08:11:41 +01:00
Florent Kermarrec
3f58df9974 platforms/targets: Fix typos. 2022-02-14 17:26:46 +01:00
Florent Kermarrec
b53b79821e platforms: Expose toolchain parameter on all platforms to ease switching to alternative/open-source toolchains. 2022-02-14 11:35:18 +01:00
Florent Kermarrec
12b91eccdc digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX). 2022-02-14 10:45:29 +01:00
Ilia Sergachev
5cd1d7eaec add openocd config for litex acorn baseboard 2022-02-13 16:44:40 +01:00
Gwenhael Goavec-Merou
5eca41ac73 targets/alinx_axu2cga: adding PS software support (inspired by xilinx_kv260) 2022-02-12 18:24:01 +01:00
Gwenhael Goavec-Merou
50654f1b7b platforms/alinx_axu2cga: add zynqmp PS configuration params 2022-02-12 18:19:55 +01:00
Gwenhael Goavec-Merou
d672d9a9b1 targets: s/alinx_axu2gca/alinx_axu2cga/gc 2022-02-12 18:12:45 +01:00
hubmartin
c2cd4410df
Code cleanup, add copyright 
Signed-off-by: hubmartin <hub.martin@gmail.com>
 2022-02-12 17:50:07 +01:00
Florent Kermarrec
c0e671919d sqrl_acorn: Downgrade to SATA Gen1 for now (allow lower sys_clk_freq and enough for current tests). 2022-02-09 19:10:12 +01:00
Florent Kermarrec
d9b77c6f25 digilent_arty: Add --flash support. 2022-02-09 17:51:56 +01:00
Florent Kermarrec
4894926c40 xilinx_kv260: +x. 2022-02-09 16:01:51 +01:00
hubmartin
27b03df886
Add Lattice ECP5 VIP board + HDMI output board support 2022-02-08 21:47:58 +01:00
Sergiu Mosanu
450a26f395 Merge branch 'master' of https://github.com/litex-hub/litex-boards 2022-02-08 12:55:09 -05:00
Sergiu Mosanu
7ed633dc4b add guideline for serial interface 2022-02-08 12:54:34 -05:00
Sergiu Mosanu
5a0f69502b enable use of HBM for linux boot 2022-02-08 12:18:38 -05:00
Arusekk
5d52bc5461
Fix seven_seg pin assignment in DE1-SoC 
Fixes quartus build error:
```
Error (171016): Can't place node "seven_seg5[6]" -- illegal location assignment PIN_AA2 File: /home/arusekk/src/fpga-proj/build/de1soc/gateware/de1soc.v Line: 49
```
 2022-02-08 09:03:53 +01:00
Florent Kermarrec
18e8bec9d4 xilinx/kv260: Minor cleanup and add Build/Use instructions (from PR). 2022-02-07 08:12:43 +01:00
enjoy-digital
8621700916
Merge pull request #345 from sergachev/feature/xilinx_kv260 
Add Xilinx KV260 support
 2022-02-07 07:53:55 +01:00
Ilia Sergachev
1d8c3789af add Xilinx KV260 support 2022-02-06 14:38:57 +01:00
Ben Stobbs
617fa26acd
Add 85F to help for orangecrab device 
The 85F orangecrab board exists, and works fine when this option is set to 85F, but leaving it out of the help is a bit confusing.
 2022-02-06 10:36:58 +00:00
Florent Kermarrec
346623fd06 trellisboard: Rename Video I2C to videoi2c. 2022-02-04 09:26:31 +01:00
Florent Kermarrec
6d4fe82179 trellisboard: Rename hdmi_i2c to i2c (to have access to i2c_scan in the BIOS). 2022-02-02 11:08:21 +01:00
Florent Kermarrec
0522d8b0c5 trellisboard: Update i2c.add_init call. 2022-02-02 10:59:54 +01:00
Florent Kermarrec
7f4d464f1b trellisboard: Add Video Terminal/Framebuffer support and use new I2C init feature to automatically configure TP410 at startup. 2022-02-02 09:52:12 +01:00
Florent Kermarrec
4251cfa865 terasic_de0nano: Add Build/Use instructions with JTAG-UART. 2022-02-01 15:58:34 +01:00
Florent Kermarrec
4d45611935 targets: Replace JTAG Atlantic (Deprecated) with JTAG-UART. 2022-02-01 11:30:26 +01:00
enjoy-digital
9144cb44fb
Merge branch 'master' into jev/deca-eth 2022-01-31 16:22:58 +01:00
Jevin Sweval
fbd424fc48 DECA: Add Ethernet and Etherbone support 
Also fixed pcf_en IO standard compared to golden Arrow project.
 2022-01-29 15:15:53 -08:00
Jevin Sweval
9e5224ca49 Add JTAGbone support to Terasic DECA 
Along the way I added UARTbone support to DECA as well for debugging.

Examples:

./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load
litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg
litex_term crossover

./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load
litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
 2022-01-27 14:13:58 -08:00
Gwenhael Goavec-Merou
dd134a4b7d digilent arty z7: allows toolchain selection (PL only) 2022-01-26 07:30:06 +01:00
Florent Kermarrec
74395ca80b digilent_nexyx_video: Add default toolchain value to CRG (to avoid breaking existing designs). 2022-01-25 16:13:57 +01:00
Florent Kermarrec
624572f2e9 alinx_axu2gca: Review and do minor cosmetic changes. 2022-01-25 14:58:47 +01:00
Gwenhael Goavec-Merou
537f04a13d alinx_axu2gca: new board 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2022-01-25 07:35:42 +01:00
Florent Kermarrec
621d45cd9e digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code. 
sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.
 2022-01-24 19:16:07 +01:00
enjoy-digital
c2276c1e6d
Merge pull request #338 from suarezvictor/master 
Add tweaks to Arty board to support yosys+nextpnr toolchain
 2022-01-24 19:02:59 +01:00
Florent Kermarrec
1abb03e514 tang_nano_4k: Review/Cleanup: 
- Revert abstractions on clk_name/period: Too much abstraction to avoid duplications makes the code more difficult to read.
ex:
  - When constraining clk27, frequency is already in the name.
  - In the target, we want to know we are using clk27 as the main clk.
  - We need a default sys_clk_freq for project only importing BaseSoC.
- Revert SPI Flash import (for consistency with other targets).
- Keep VexRiscv as default CPU since this target is able to run it and also for consistency with other targets.
 2022-01-24 18:46:51 +01:00
enjoy-digital
e357eb6d8f
Merge pull request #337 from sergachev/tang_nano_4k_emcu 
Enable LiteX BIOS on ARM core on Tang nano 4K
 2022-01-24 18:36:10 +01:00
Florent Kermarrec
cc1b46f106 tang_nano_9k: Fix HyperRAM integration. 2022-01-24 18:35:12 +01:00
Victor Suarez Rovere
db77ea5c7a Add tweaks to Arty board to support yosys+nextpnr toolchain 2022-01-24 02:06:34 -03:00
Ilia Sergachev
f078e55bb1 tang nano 4k: fix removed default_clk_period, fix do_finalize signature 2022-01-23 16:47:20 +01:00
Ilia Sergachev
6238052b10 tang nano 4k: disable spi flash with gowin emcu, cleanup 2022-01-23 16:10:46 +01:00
Ilia Sergachev
6c81fc708c tang nano 4k: add memory regions, set default cpu 2022-01-23 13:05:51 +01:00
enjoy-digital
787f44e7d9
Merge pull request #336 from tcal-x/cmod-a7-flash 
Digilent CMOD A7: add flash support.
 2022-01-23 08:36:49 +01:00
Tim Callahan
6567af6f49 Digilent CMOD A7: add flash support. 
Add both "--flash" and "--with-spi-flash"; tested on board.
4MB flash mapped at 0x00400000.

Signed-off-by: Tim Callahan <tcal@google.com>
 2022-01-22 18:50:12 -08:00
Icenowy Zheng
f533e7f8ba sipeed_tang_nano_9k: enable copackaged PSRAM 
Also enable SPI SDCard which was pending by the lack of main_ram
previously.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2022-01-23 03:37:03 +08:00
Florent Kermarrec
e35b9b439f platforms/sipeed_tang_nano_9k: Fix copyrights and remove board diagram/description of the 4k. 2022-01-22 15:55:36 +01:00