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Fin Maaß 362a28b72a
efinix: fix reset 
fix reset on all efinix boards.
To reset the PLL a pulse is needed, which
has to be driven by a clock that is
not generated by the PLL.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 13:51:09 +02:00
..
__init__.py Move import Compat directly to litex_boards.__init__.py and simplify. 2021-03-25 16:47:47 +01:00
adi_adrv2crr_fmc.py di_adrv2crr_fmc: Bump PCIe to 8 lanes 2024-02-05 11:43:02 +01:00
adi_plutosdr.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
alchitry_au.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alchitry_cu.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
alchitry_mojo.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
alientek_davincipro.py targets: +x on missing targets. 2024-09-20 13:03:17 +02:00
aliexpress_xc7k70t.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
aliexpress_xc7k420t.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alinx_ax7010.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alinx_axau15.py targets/alinx_axau15: Remove unwanted add_sdcard() call. 2024-04-23 11:40:01 +02:00
alinx_axu2cga.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
analog_pocket.py target/analog_pocket: Remove debug (Will be investigated externally). 2023-10-27 15:32:36 +02:00
antmicro_artix_dc_scm.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
antmicro_datacenter_ddr4_test_board.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
antmicro_lpddr4_test_board.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
antmicro_sdi_mipi_video_converter.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
arduino_mkrvidor4000.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
avnet_aesku40.py avnet_aesku40: Expose ethernet/etherbone parameters. 2023-06-13 09:26:07 +02:00
berkeleylab_marble.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
camlink_4k.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
colognechip_gatemate_evb.py adding colognechip_gatemate_evb 2024-02-28 17:27:21 +01:00
colorlight_5a_75x.py target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
colorlight_i5.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
colorlight_i9plus.py colorlight_i9plus: Switch to OpenFPGALoader for loading bitstreams. 2024-04-02 08:44:25 +02:00
decklink_intensity_pro_4k.py targets/CRG: Add rst signal when missing. 2023-07-26 16:56:27 +02:00
decklink_mini_4k.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
decklink_quad_hdmi_recorder.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
digilent_arty.py #570: Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007. 2024-07-05 10:26:28 +02:00
digilent_arty_s7.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_arty_z7.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
digilent_atlys.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_basys3.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_cmod_a7.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
digilent_genesys2.py #570: Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007. 2024-07-05 10:26:28 +02:00
digilent_netfpga_sume.py targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets. 2024-09-20 13:09:48 +02:00
digilent_nexys4.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
digilent_nexys4ddr.py boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg 2024-09-13 15:40:12 +02:00
digilent_nexys_video.py targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use. 2023-11-07 13:22:30 +01:00
digilent_pynq_z1.py targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU 2024-06-19 07:59:24 +02:00
digilent_zedboard.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
ebaz4205.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
efinix_t8f81_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_ti375_c529_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_titanium_ti60_f225_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_trion_t20_bga256_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_trion_t20_mipi_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_trion_t120_bga576_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
efinix_xyloni_dev_kit.py efinix: fix reset 2024-10-08 13:51:09 +02:00
ego1.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
enclustra_mercury_kx2.py targets/enclustra: Add Enclustra to identifier. 2024-07-22 11:38:22 +02:00
enclustra_mercury_xu5.py targets/enclustra: Add Enclustra to identifier. 2024-07-22 11:38:22 +02:00
enclustra_mercury_xu8_pe3.py targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe. 2024-07-22 11:40:19 +02:00
fairwaves_xtrx.py targets/CRG: Add rst signal when missing. 2023-07-26 16:56:27 +02:00
fpc_iii.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
fpgawars_alhambra2.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
gadgetfactory_papilio_pro.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
gsd_butterstick.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
gsd_orangecrab.py gsd_orangecrab: Add --without_dfu_rst argument to allow disabling reset to DFU on Button press. 2024-03-11 17:23:42 +01:00
hackaday_hadbadge.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
hseda_xc7a35t.py targets: +x on missing targets. 2024-09-20 13:03:17 +02:00
ice_v_wireless.py targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM. 2024-08-28 15:53:53 +02:00
icebreaker.py targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM. 2024-08-28 15:53:53 +02:00
icebreaker_bitsy.py targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM. 2024-08-28 15:53:53 +02:00
isx_im1283.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
jungle_electronics_fireant.py efinix: fix reset 2024-10-08 13:51:09 +02:00
kosagi_fomu.py targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM. 2024-08-28 15:53:53 +02:00
kosagi_netv2.py boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg 2024-09-13 15:40:12 +02:00
krtkl_snickerdoodle.py targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU 2024-06-19 07:59:24 +02:00
lambdaconcept_ecpix5.py targets/lambdaconcept_ecpix5.py: allows configuring eth_ip/remote_ip/dynamic 2024-06-14 15:58:25 +02:00
lattice_certuspro_nx_evn.py targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR 2024-07-22 15:18:27 +02:00
lattice_certuspro_nx_vvml.py targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR 2024-07-22 15:18:27 +02:00
lattice_crosslink_nx_evn.py targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR 2024-07-22 15:18:27 +02:00
lattice_crosslink_nx_vip.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
lattice_ecp5_evn.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
lattice_ecp5_vip.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
lattice_ice40up5k_evn.py targets: Map SPRAM to SRAM when use as SRAM. 2024-07-17 11:01:34 +02:00
lattice_versa_ecp5.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
limesdr_mini_v2.py targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart 2024-04-11 15:12:17 +02:00
linsn_rv901t.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
litex_acorn_baseboard.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
litex_acorn_baseboard_mini.py targets/litex_acorn_baseboard_mini: Add detect_ftdi_chip method since newer batch of baseboard is mounted with FTDI ft4232 chips. 2024-07-19 15:43:25 +02:00
logicbone.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
machdyne_konfekt.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_kopflos.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_krote.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
machdyne_lakritz.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_minze.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_ml1.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_ml2.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_mx1.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_mx2.py add support for Mozart MX2 2024-10-05 08:16:18 +02:00
machdyne_noir.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_schoko.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
machdyne_vanille.py targets/machdyne_vanille: set uart_name to stub 2024-06-22 12:13:30 +02:00
machdyne_vivaldi_ml1.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
micronova_mercury2.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
mist.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
mnt_rkx7.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
muselab_icesugar.py targets: Map SPRAM to SRAM when use as SRAM. 2024-07-17 11:01:34 +02:00
muselab_icesugar_pro.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
myminieye_runber.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
newae_cw305.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
numato_aller.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
numato_mimas_a7.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
numato_nereid.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
numato_tagus.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
ocp_tap_timecard.py targets/pcie: Update Xilinx S7 constraints. 2023-03-06 12:20:34 +01:00
olimex_gatemate_a1_evb.py Olimex GateMate A1 EVB: new Board 2024-03-02 12:23:27 +01:00
opalkelly_xem8320.py opalkelly_xem8320: Review and update to recent LiteX changes. 2023-03-01 09:16:51 +01:00
pano_logic_g2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_5cefa2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_5cefa5.py qmtech altera boards: sdram io properties for more speed 2024-03-30 20:43:41 +07:00
qmtech_10cl006.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_artix7_fbg484.py qmtech_artix7_fgg676: fix wrong memory chip type 2024-03-29 08:41:19 +07:00
qmtech_artix7_fgg676.py qmtech_artix7_fgg676: fix wrong memory chip type 2024-03-29 08:41:19 +07:00
qmtech_ep4ce15_starter_kit.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
qmtech_ep4cex5.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_ep4cgx150.py qmtech altera boards: sdram io properties for more speed 2024-03-30 20:43:41 +07:00
qmtech_kintex7_devboard.py target/qmtech_kintex7_devboard: +X. 2024-02-26 15:41:09 +01:00
qmtech_wukong.py qmtech_wukong: Switch to direct instance of LiteEthPHYGMII since hybrid MII/GMII does not seems to work correctly. 2024-03-28 16:02:55 +01:00
qmtech_xc7a35t.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
qmtech_xc7k325t.py QMTech XC7K325T: use the buttons on the core board 2024-02-28 04:40:17 +07:00
quicklogic_quickfeather.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
qwertyembedded_beaglewire.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
radiona_ulx3s.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
radiona_ulx4m_ld_v2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
rcs_arctic_tern_bmc_card.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
redpitaya.py targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU 2024-06-19 07:59:24 +02:00
rz_easyfpga.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
saanlima_pipistrello.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
scarabhardware_minispartan6.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
seeedstudio_spartan_edge_accelerator.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
siglent_sds1104xe.py siglent_sdr1104xe: Update IP/MAC addresses. 2024-07-02 17:09:23 +02:00
signaloid_c0_microsd.py targets: +x on missing targets. 2024-09-20 13:03:17 +02:00
simple.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
sipeed_tang_mega_138k_pro.py sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module 2024-08-04 12:13:47 +02:00
sipeed_tang_nano.py WIP: make boards Gowin boards work with Apicula 2024-09-04 08:33:06 +02:00
sipeed_tang_nano_4k.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
sipeed_tang_nano_9k.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
sipeed_tang_nano_20k.py WIP: make boards Gowin boards work with Apicula 2024-09-04 08:33:06 +02:00
sipeed_tang_primer.py targets/CRG: Add rst signal when missing. 2023-07-26 16:56:27 +02:00
sipeed_tang_primer_20k.py boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg 2024-09-13 15:40:12 +02:00
sipeed_tang_primer_25k.py WIP: make boards Gowin boards work with Apicula 2024-09-04 08:33:06 +02:00
sitlinv_a_e115fb.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
sitlinv_stlv7325_v1.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
sitlinv_stlv7325_v2.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
sitlinv_xc7k420t.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
sqrl_acorn.py targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman). 2023-09-27 11:06:50 +02:00
sqrl_fk33.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
sqrl_xcu1525.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_de0nano.py targets: Switch to openocd_usb_blaster/2.cfg. 2023-09-21 09:16:24 +02:00
terasic_de1soc.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_de2_115.py terasic_de2_115: Cosmetic cleanup. 2023-11-06 19:21:53 +01:00
terasic_de10lite.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_de10nano.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_deca.py target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
terasic_sockit.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
tinyfpga_bx.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
trellisboard.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_c10lprefkit.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
trenz_cyc1000.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_max1000.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_te0725.py targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). 2024-09-04 22:06:40 +02:00
trenz_tec0117.py Update tec0117 to work with Apicula 2024-10-04 15:25:39 +02:00
tul_pynq_z2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_ac701.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_alveo_u200.py Fix Memory initialization of Alveo U200 failed #1606 2023-04-17 18:59:50 +07:00
xilinx_alveo_u250.py Fix Memory test failure of Alveo U250 2023-04-24 17:35:58 +09:00
xilinx_alveo_u280.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
xilinx_kc705.py xilinx_kc705: Minor Cleanup/Update. 2024-03-27 08:48:05 +01:00
xilinx_kcu105.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_kv260.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
xilinx_vc707.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_vcu118.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_vcu128.py targets: +x on alchitry_cu and vcu128. 2023-07-06 13:29:35 +02:00
xilinx_zc706.py platforms,targets/xilinx_zc706: added choice between vivado(default) and openFPGALoader, re-enable DDR 2024-04-08 20:38:09 +02:00
xilinx_zcu102.py targets/xilinx_zcu102: Add litedram to the target. 2023-10-14 00:00:26 +09:00
xilinx_zcu104.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_zcu106.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_zcu216.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
xilinx_zybo_z7.py targets: Use KILOBYTE/MEGABYTE constants when possible. 2024-08-29 12:18:19 +02:00
ztex213.py targets/CRG: Add rst signal when missing. 2023-07-26 16:56:27 +02:00