de9d3ab314
soc/cores/cpu/urv: Add DataBusToWishbone and use it.
2024-11-06 21:59:11 +01:00
2b3913982c
soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.
2024-11-06 21:49:39 +01:00
d8e168a81f
Enhance software build performance by utilizing all available CPU cores in the builder
2024-11-06 11:35:28 -08:00
935326e66c
Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD
2024-11-06 11:25:54 -08:00
1204cfda9d
soc/cores/cpu/urv: Fix add_sources.
2024-11-05 17:33:32 +01:00
20b0e98fe0
cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.
2024-11-05 17:19:13 +01:00
e9613499ea
Fix SOC region range check
2024-11-04 12:01:29 -08:00
0170462fe8
soc/cores/jtag: Fix/Test p_init/p_INIT workaround.
2024-11-04 14:34:28 +01:00
3f3249cdf0
Merge pull request #2113 from trabucayre/toolchain_diamond_sdc
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litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:53:48 +01:00
47e8b0273f
litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:42:38 +01:00
175e63ac4c
soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.
2024-11-04 12:40:39 +01:00
61ab30a739
soc/cores/jtag: Revert p_INIT since not tested.
2024-10-28 20:05:47 +01:00
10184ad325
Merge pull request #2097 from trabucayre/build_diamond_addition
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Build diamond addition
2024-10-28 20:05:01 +01:00
dd092863f8
Merge branch 'master' into vexiiriscv-macsg
2024-10-28 20:02:56 +01:00
18714dfca3
Merge pull request #2104 from andelf/fix/ws2812-of-1-led
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Fixes #2103 : calculate memory depth for WS2812
2024-10-28 19:53:25 +01:00
59fc1caac4
Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi
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vexiiriscv: add options and conditions
2024-10-25 14:26:02 +02:00
773fb34079
vexiiriscv: have opensbi behind a option
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this way opensbi things are only activated,
when a linux variant is used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-25 13:40:20 +02:00
8c7e510473
Fixes #2103 : calculate memory depth for WS2812
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See-also: https://github.com/m-labs/migen/pull/295
2024-10-25 11:48:57 +08:00
24db36ced5
Merge remote-tracking branch 'origin/master' into wuff
2024-10-24 16:02:52 +02:00
375940ad7d
soc/core/vexiiriscv: add macsg support (dma based ethernet)
2024-10-24 16:00:51 +02:00
d7bf75a75c
bios: litespi: add newline to debug output
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add newline to debug output
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:12:12 +02:00
63fa4fda85
bios: litespi: clear rx queue after write
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clear rx queue at the end of spiflash_master_write().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:10:37 +02:00
54973eb9cb
build: efinix: use constant output option
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use constant output option, when the output is a `Constant`
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 14:12:30 +02:00
2d96e99494
build: io: SDRTristate: move check
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check wraped signals instead of before.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:18:57 +02:00
70f4a349e5
efinix: ifacewriter: fix in output
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fix in OUTPUT
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:10:16 +02:00
d6eec8e76d
efinix: ifacewriter: gpio: share common code
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share common code for INPUT, INOUT and OUTPUT.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:08:58 +02:00
aab8912f5a
soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.
2024-10-17 17:44:40 +02:00
9449d25911
soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
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- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
2024-10-17 16:54:20 +02:00
edb56e73aa
soc/cores/cpu: Add initial uRV CPU support (not yet working).
2024-10-16 22:24:07 +02:00
06f9f9780d
litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fails with diamond)
2024-10-16 13:47:42 +02:00
ea81314866
build/lattice/diamond.py,platform.py: allows adding custom strategy
2024-10-16 13:46:43 +02:00
331e1938c9
build/lattice/diamond.py,platform.py: allows adding lattice's IPs
2024-10-16 13:45:57 +02:00
c4943c1c5d
build/lattice/diamond.py: allows adding addition ldf commands in tcl
2024-10-16 13:44:20 +02:00
d5e4f9e975
soc/core/vexiiriscv : bring back xilinx support
2024-10-15 09:36:32 +02:00
7f04cafe08
soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII
2024-10-10 17:28:29 +02:00
2935b7afb1
soc/cores/cpu/zynqmp/core.py: added missing pps signals
2024-10-10 17:26:35 +02:00
ddb8d16381
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support
2024-10-09 16:14:31 +02:00
d26994916d
build: efinix: use ifacewriter to set bank voltage
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use efinix python api to set bank voltage,
instead of editing the peri.xml file.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 09:05:04 +02:00
9ad5d21231
Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix
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build: efinix: Tristate fix
2024-10-07 11:06:26 +02:00
4fcae9f3c7
build: efinix: Tristate fix
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fix efinix Tristate by adding size to add_iface_io().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-07 10:15:38 +02:00
64cf925b39
soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.
2024-10-02 17:10:08 +02:00
5e897752b7
soc/intergration/soc/add_pcie: Add new status_width parameter.
2024-10-02 17:10:05 +02:00
c1733ea2ff
build: io: make oe2 of DDRTristate optional
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make oe2 of DDRTristate optional.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-01 12:11:27 +02:00
280b6b4ee4
build: io: don't use mutable object as default value
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don't use mutable object (here: ClockSignal()) as default value,
beacuse they will be the same object.
Leeds to problems, when for example two `SDRInput`
are used in two different Modules and one of them is
used with a `ClockDomainsRenamer()`, then both are changed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-30 15:18:11 +02:00
2130ff2fb3
build/efinix/efinity: Cosmetic cleanup on toolchain arguments.
2024-09-26 18:06:36 +02:00
1568b25ff7
build/efinix/common: Cosmetic cleanups.
2024-09-26 18:03:36 +02:00
431feb0ac2
build/efinix/common: Enable back SDRInput since support fixed with recent changes.
2024-09-26 18:01:02 +02:00
9760493c32
build/efinix/common: Switch to LiteXModule.
2024-09-26 17:46:07 +02:00
95e5e7302e
Merge pull request #2083 from VOGL-electronic/efinix_common_improve
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build: efinix: EfinixTristateImpl: use GPIO Bus
2024-09-26 17:41:07 +02:00
a825c61385
build: efinix: EfinixTristateImpl: use GPIO Bus
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use the gpio bus for Efinix Tristate implemenation.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
e9a4b178ce
build: efinix: platform.py: add `get_pins_location` and `get_pins_name`
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add `get_pins_location` and `get_pins_name`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
f8dc03810d
build: efinix: use LiteXContext to get platform
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use LiteXContext to get platform.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:41 +02:00
afcc477c4e
efinix: common: replace `is_inclk_inverted`
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replace `is_inclk_inverted` with `in_clk_inv` and `out_clk_inv`.
This way thwe right prop is set in the ifacewriter.py.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:11:39 +02:00
a605e75873
efinix: ifacewriter: remove deprecated GPIO properties
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removes `OE_CLK_PIN_INV` and `OE_CLK_PIN` as they
got deprecated in efinity 2023.1.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
2c3536720c
efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block
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add `in_clk_inv` for GPIO INPUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
10ab1b76c0
efinix: ifacewriter: fix `out_reg` in GPIO INOUT block
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fix `out_reg` in GPIO INOUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
b135f71512
build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.
2024-09-26 12:58:54 +02:00
b5e91473b7
build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.
2024-09-26 11:50:37 +02:00
0e337e2079
Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input
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build: efinix: common.py; add `SDRInput`
2024-09-26 11:43:20 +02:00
a19fbb70c4
Merge pull request #2078 from VOGL-electronic/efinix_add_ipm
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build: efinix: add function to add ip
2024-09-26 11:42:34 +02:00
b11cc8c3eb
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
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Efinix iface signal names.
2024-09-26 11:42:02 +02:00
39d292a3c7
build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.
2024-09-26 10:38:05 +02:00
a3a55fc8fb
build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.
2024-09-26 10:14:42 +02:00
fde9d2e4ad
build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
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Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.
2024-09-26 10:13:58 +02:00
61f715e6e7
build: efinix: common.py; add `SDRInput`
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add `SDRInput` for efinix
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:17:53 +02:00
c3e87367c3
soc/cores/vexriscv_smp: Add the generation of the default sim config ( https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405 )
2024-09-25 10:38:37 +02:00
b86d76baed
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.
2024-09-25 08:56:51 +02:00
8a6264c4f6
build: efinix: add function to add ip
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add function to add efinix IP.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-24 11:59:28 +02:00
c95a6e041c
soc/interconnect/stream: Add Delay module.
2024-09-23 12:23:29 +02:00
baff4c69fe
Merge pull request #2075 from trabucayre/efinix_clkinput_signal
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build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 11:59:06 +02:00
033ec13f08
Merge pull request #2076 from trabucayre/xc7s_jtag
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Spartan7 jtag support
2024-09-19 11:53:55 +02:00
6e9dffdbf5
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado).
2024-09-19 11:10:51 +02:00
ad2c3fcea7
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant.
2024-09-19 09:21:13 +02:00
f1e1f3530e
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)
2024-09-19 09:14:30 +02:00
aca959b059
build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 09:12:36 +02:00
e072156b93
build/xilinx/platform.py: added xc7s to the list of device supporting jtag access
2024-09-19 06:49:44 +02:00
fc68f031a1
soc/cores/jtag.py: added Spartan7 definition for BSCANE2
2024-09-19 06:49:10 +02:00
9bacbe130b
Merge pull request #1974 from motec-research/dts_zephyr_updates
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DTS zephyr updates
2024-09-17 14:58:51 +02:00
a350d2e909
soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux.
2024-09-13 19:21:26 +02:00
2a19a61e05
build/xilinx/vivado: Fix typo.
2024-09-13 10:39:13 +02:00
99550809b3
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet
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sim: add HW_PREAMBLE_CRC for ethernet
2024-09-13 08:36:40 +02:00
dc8c1bd9cd
build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives.
2024-09-12 18:04:25 +02:00
203c9816b2
integration/soc/add_etherbone: Allow 64-bit support now that validated.
2024-09-12 13:39:13 +02:00
2fd8c2cd61
sim: add HW_PREAMBLE_CRC for ethernet
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This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble
is automatically attached by the tap, there is no need to add it from
the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-09-12 10:07:43 +02:00
b41a526e81
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac
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soc.py: add_ethernet: add mac addr constant
2024-09-11 11:54:14 +02:00
11c7b69fd4
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix
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bios: boot.c: fix warnings
2024-09-11 11:53:52 +02:00
7b3f1509d1
soc.py: add_ethernet: add mac addr constant
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add mac addr constant to add_ethernet,
so it matches the one from add_etherbone.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:21:53 +02:00
3966e3438c
bios: boot.c: fix warnings
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this fixes the warnings, when compiling.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:15:56 +02:00
dc8b74cc58
Merge pull request #2060 from Dolu1990/efinix-rework
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build/efinix: add a few IO primitives, IO constraints, sdc rework
2024-09-10 18:40:10 +02:00
a80f290d80
soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name
2024-09-10 18:07:34 +02:00
ad09ffc150
soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str
2024-09-10 18:03:12 +02:00
109ae17e9e
build/efinix/common.py: replaced i as str by a ClockDomain
2024-09-10 17:56:49 +02:00
458e0057f2
soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.
2024-09-09 18:24:14 +02:00
5cd1a57080
soc/interconnect/wishbone: Cosmetic cleanup on Cache.
2024-09-09 18:16:40 +02:00
e06045c576
Merge pull request #2059 from Dolu1990/vexii-clk-video
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soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-09 14:12:50 +02:00
2db93c8e78
core/vexiiriscv: improve l2 timings
2024-09-06 16:07:05 +02:00
bd03c496a1
bios: add spiram
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add spiram in bios, so it can enable QPI.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-05 16:31:32 +02:00
599c6dde37
litex/build/efinix/common.py add EfinixDDRTristate binding
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Co-authored-by: Fin Maaß <info@finmaass.de>
2024-09-05 16:12:32 +02:00
c0fddb6561
build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled
2024-09-05 15:21:12 +02:00
642cfbe9a7
soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-05 15:16:15 +02:00
Florent Kermarrec
Long Pham
Chris Keilbart
Gwenhael Goavec-Merou
Dolu1990
Fin Maaß
Andelf
Matthias Breithaupt