e62d84b77b
Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support"
...
This reverts commit 0ea6dd91aafa47c62b6d
2024-09-05 15:15:49 +02:00
0ea6dd91aa
soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-05 15:14:46 +02:00
f512c65077
vexiiriscv git update
2024-09-05 13:17:22 +02:00
2190ca403a
core/usb_ohci: fix SDRTristate clock
2024-09-05 10:24:45 +02:00
f67b39739e
soc/integration/add_ethernet: Expose full_memory_we parameter.
2024-09-05 10:18:12 +02:00
1f2418de3b
core/usb_ohci: fix SDRTristate clock
2024-09-05 10:17:22 +02:00
84e7e816c7
efinix: pll now force the generated clock into cd.clk *WARNING*
2024-09-05 10:16:43 +02:00
d3161ad74c
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-09-04 14:42:45 +02:00
d0215001f4
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
2024-09-03 17:47:40 +02:00
a90ab9dcca
efinix: Merge pt.sdc to the litex sdc to get constraints right
2024-09-03 12:05:26 +02:00
4152d22065
Revert "build/efinix/platform: fix get_pin_name()"
...
This reverts commit 0cb101da25
2024-09-03 10:24:38 +02:00
3de5832b9c
vexiiriscv: Now use pll.locked for debug reset
2024-09-03 07:58:24 +02:00
19b3f24d9f
efinix: ifacewriter support drive strength and slew
2024-09-03 07:57:30 +02:00
e01ce6f948
efinix: ifacewriter support drive strength and slew
2024-09-03 07:55:25 +02:00
babe233407
build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software)
2024-09-01 09:55:01 +02:00
3da470048a
build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model
2024-09-01 09:53:24 +02:00
2f2b292e06
vexii add with-cpu-clk
2024-08-30 18:16:56 +02:00
15cd556750
Merge pull request #2053 from enjoy-digital/hyperram_new
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soc/cores/hyperbus: Full rewrite of HyperRAM core.
2024-08-30 15:38:59 +02:00
61b54aa491
soc/integration/soc: Fix add_peripheral.
2024-08-30 12:08:00 +02:00
c554752e8a
soc/cores/hyperbus: Add automatic read burst detection.
2024-08-30 11:53:14 +02:00
c14f1d0816
vexiiriscv add video support
2024-08-30 10:44:36 +02:00
5fb873d209
efinix: Add support for more IO
2024-08-30 10:44:10 +02:00
3bde3e9848
soc/cores/hyperbus: Add automatic write burst detection.
2024-08-29 19:20:23 +02:00
fac80c3a51
soc/cores/hyperbus: Full rewrite of HyperRAM core.
...
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.
This rewrite provides a base for future development.
2024-08-29 12:54:09 +02:00
cc3f13670a
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
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efinix: Fix PLL with external clock input ifacewriter
2024-08-28 20:13:03 +02:00
d4003b8cfa
efinix add SCHMITT_TRIGGER support
2024-08-28 19:59:30 +02:00
4ded509444
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
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efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:50:04 +02:00
6d46a5ba05
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:02:58 +02:00
0fcc27f58f
build/colognechip/colognechip.py: simplify constrains file with the new toolchain
2024-08-24 12:20:58 +02:00
07e11858c6
soc/cores/clock/colognechip.py: rework/fix locked signal
2024-08-24 12:19:34 +02:00
ef775e0b8e
Merge pull request #2043 from pepijndevos/moreapicula
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fixes for apicula support
2024-08-24 10:37:17 +02:00
4400fbb966
Apicula: add GWINR-18 aliases
2024-08-22 16:02:41 +02:00
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
2024-08-21 17:10:36 +02:00
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
2024-08-21 15:35:21 +02:00
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
2024-08-21 12:07:55 +02:00
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
2024-08-21 11:50:46 +02:00
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
2024-08-21 11:41:13 +02:00
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
2024-08-21 11:17:55 +02:00
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
2024-08-21 10:57:36 +02:00
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
...
Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
2024-08-20 14:58:51 +02:00
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
2024-08-20 14:44:33 +02:00
bfe000150c
soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.
2024-08-20 14:25:23 +02:00
7b413352c2
soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
2024-08-20 12:04:23 +02:00
8f5c2dfbca
soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).
2024-08-20 12:03:40 +02:00
3a53a92bb2
soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.
2024-08-20 11:38:33 +02:00
9c1958d692
soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.
2024-08-20 11:26:58 +02:00
c1403db407
json2dts_zephyr: omit disable handler
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omit disable handler for the sdcard peripherals,
as they still don't have a driver in zephyr and are not in the board dts.
This way the build in zephyr will not fail.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-20 11:23:21 +02:00
db86ec08b8
soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
2024-08-20 11:12:17 +02:00
1f71f3d68b
soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
2024-08-20 10:40:24 +02:00
a960dc33bc
soc/cores/hyperbus: Minor cleanup changes.
2024-08-20 10:26:34 +02:00
b95b66b554
soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).
2024-08-20 10:10:53 +02:00
c5416f1680
fixes for apicula support
2024-08-19 19:54:26 +02:00
afc66fd5cf
cores/picorv32: Fix idbus.sel for reads.
2024-08-19 13:34:50 +02:00
6623a5b691
Merge pull request #2028 from VOGL-electronic/spi_ram_add
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soc: add add_spi_ram function
2024-08-16 19:08:48 +02:00
039be2a248
add dual use gpio options
2024-08-16 15:56:24 +02:00
dc3f2d6421
Add missing license header to apicula.py
2024-08-15 01:54:31 +02:00
623536cd6a
Remove empty build_timing_constraints override in GowinApiculaToolchain
2024-08-15 01:52:22 +02:00
e0968b3574
Adds apicula toolchain to gowin platform
2024-08-12 06:55:11 +02:00
3d0fe4ebca
Fix litex.build.gowin's __init__.py; closes #2034
2024-08-11 05:44:14 +02:00
3cd820974a
build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)
2024-08-04 09:39:46 +02:00
cd457c9809
soc: add l2 cache to spi_ram
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Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
e29dc39377
openocd/jtagspi: Allow users to specify additional init commands
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This change makes it possible to e.g. use flahs chips that would not be correctly detected by OpenOCD.
All that has to be done is to add `init_commands=["jtagspi set 0 \"name\" {size} {pagesize} {read_cmd} 0 {pprg_cmd} {mass_erase_cmd} {sector_size} {sector_erase_cmd}"]`.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
41b346d141
bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)
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Instead of reading each individual byte, causing multiple 4-byte requests to each address, this
change results in a single read for each address.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
03a0a6fd9b
soc: add add_spi_ram function
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Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
1f6673c6eb
build/altera/common.py: implement SDRTristate for Agilex5 family
2024-07-30 16:36:05 +02:00
e19dfa8800
tools/litex_json2dts_zephyr: fix reg format
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addr size pairs should be enclosed '< >' and comma separated to be
dts compliant.
2024-07-29 09:16:59 +10:00
2776b63d1a
tools/litex_json2dts_zephyr: improve indentation
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To support linux dts generation.
2024-07-29 09:16:59 +10:00
3041150773
Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special
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build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-26 18:26:19 +02:00
ba8830e6cd
global: Remove @trabucayre's tracers :)
2024-07-26 12:57:01 +02:00
5c5bc82f22
interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.
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Needs to be filtered on param_fifo.sink.ready and not payload_fifo.sink.ready.
2024-07-26 11:52:17 +02:00
dc04949d78
build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-25 14:11:06 +02:00
c51d22074f
soc/integration/soc/add_uart: Allow directly passing uart_pads.
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Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
2024-07-22 16:23:22 +02:00
b8cb6da2b9
soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output
2024-07-22 15:11:40 +02:00
ecd0f0e548
cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.
2024-07-22 14:24:34 +02:00
4662b95f16
Merge pull request #2012 from machdyne/master
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soc/cores/video: Add additional color formats
2024-07-21 09:34:00 +02:00
f99658200e
soc/cores/i2c: rewrite state machine
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* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
2024-07-20 15:45:44 +10:00
dce152b348
soc/cores/i2c: change SDA 1 or 2 cycles earlier
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* update 'only change SDA when SCL is stable' to max 1 sys_clk delay
2024-07-20 15:45:44 +10:00
e36946b251
soc/cores/i2c: convert to LiteXModule and name some components
2024-07-20 15:45:44 +10:00
c867d5647b
soc/cores/i2c: only change SDA when SCL is stable
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Avoid changing SDA immediately in states WRITE0 and READ0 to guarantee SDA hold is > 0
2024-07-20 15:45:44 +10:00
aef6cb3103
soc/cores/i2c: remove unnecessary code
2024-07-20 15:45:44 +10:00
5504cc626f
soc/cores/i2c: change ISR to rising edge of idle
2024-07-20 15:45:44 +10:00
b8b6ecef7c
soc/cores/i2c: fix CSR generation
2024-07-20 15:45:44 +10:00
ad37e17743
soc/cores/i2c: add interrupt
2024-07-20 15:45:44 +10:00
a079da922a
soc/cores: adapt misoc i2c to litex
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Also add misoc license information.
2024-07-20 15:45:44 +10:00
9dc3eefb7d
soc/cores/i2c: import from misoc
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* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
2024-07-20 15:45:44 +10:00
a014c4f07c
tools/litex_sim: Cleanup imports.
2024-07-18 12:16:23 +02:00
cbe7413fee
Fix VexiiRiscv
2024-07-18 11:32:07 +02:00
f687425cb1
Update VexiiRiscv
2024-07-18 11:26:13 +02:00
9fa1b4c123
Update Nax/Vexii
2024-07-12 16:17:30 +02:00
aef5a2094e
soc/cores/video: Add additional color formats
2024-07-10 15:21:51 +02:00
22ff3ac42d
Merge branch 'master' into vexiiriscv
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# Conflicts:
# litex/soc/cores/cpu/vexiiriscv/core.py
2024-07-10 09:37:43 +02:00
1267ba8ae6
Update Nax/Vexii
2024-07-10 09:35:34 +02:00
e4e9bd2125
interconnect/axi/axi_lite: Add bursting property even if always False.
2024-07-09 17:02:54 +02:00
372ab25273
Merge branch 'nax64_irq' into vexiiriscv
2024-07-09 15:18:25 +02:00
549d23e4f7
build/efinix: Add default parameter values and fix other typos.
2024-07-09 10:04:03 +02:00
e6171e79db
build/efinix: Fix typos (thanks @AndrewD).
2024-07-09 10:00:21 +02:00
ec1528fb69
build/efinix: added argument to change synthesis options configurations
2024-07-08 15:59:30 +02:00
0db650ac6a
soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic).
2024-07-05 13:56:14 +02:00
3c2ddd1655
cores/can/ctu_can_fd: Remove pads.irq that was used as debug.
2024-07-05 09:34:36 +02:00
7ec35eb4c5
Merge pull request #2007 from enjoy-digital/ctu-can-fd
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Add initial CTU-CAN-FD core support.
2024-07-05 09:16:21 +02:00
d838a9ca73
Merge pull request #2006 from trabucayre/update_altera_build
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Update altera build
2024-07-04 13:04:15 +02:00
9fd63973aa
build/altera/quartus.py: added support for ips other than QSYS_FILE
2024-07-04 09:51:09 +02:00
7393c35264
build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn
2024-07-04 09:50:06 +02:00
b286fe5621
Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs
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litex_json2dts_zephyr.py: Remove unnessesary configs
2024-07-04 09:10:27 +02:00
d4d1a1bfd7
gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.
2024-07-03 21:44:31 +02:00
aac828b4cb
soc/add_etherbone: Update ethmac.
2024-07-02 17:10:32 +02:00
b285992fb1
litex_json2dts_zephyr.py: Remove unnessesary configs
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Remove all configs, that are enabled by default
in zephyr based on the devicetree.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-07-02 15:04:50 +02:00
2a83bce63e
cores/dma: Automatically call add_ctrl method in add_csr is ctrl are not present.
2024-07-01 18:22:41 +02:00
9c07b45f3c
soc/add_ethernet: Add 64-bit data_width support.
2024-06-27 09:35:28 +02:00
4b745f9eba
soc/cores/dma: Add default parameters to add_ctrl.
2024-06-26 17:57:47 +02:00
01a15e4bbf
soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic.
2024-06-26 16:13:45 +02:00
23a0d8fa2a
soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic.
2024-06-26 16:07:12 +02:00
14a640302c
integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac.
...
LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161 .
2024-06-25 17:39:26 +02:00
1ad0f828bb
soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design.
2024-06-25 15:07:37 +02:00
462016a1d0
litex/tools/litex_json2dts_linux: Add initial CAN support.
2024-06-24 13:01:18 +02:00
71ff4eaadc
soc/cores/can: Switch to our fork of CTU-CAN-FD, remove debug signals and do a git clone if not present in execution directory.
2024-06-24 12:53:38 +02:00
bad64bcf6d
soc/cores: Add initial CTU-CAN-FD integration from 2021 work with recent updates/tests.
2024-06-24 12:27:17 +02:00
a47dde6fbc
Merge pull request #1999 from FlyGoat/csr-re
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csr_bus: Honour re signal from the upstream bus
2024-06-24 10:36:48 +02:00
8e4f8781f7
Merge pull request #1996 from VOGL-electronic/litex_watchdog
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core: add watchdog feature
2024-06-24 10:32:48 +02:00
11537ec8cc
Merge pull request #2001 from rtucker85/master
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liblitespi: fix xor-used-as-pow bug
2024-06-24 09:05:34 +02:00
21674ee29c
Merge pull request #1998 from FlyGoat/ahb-fixes
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soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
2024-06-24 09:04:33 +02:00
fd5a01dd26
integration/soc: Cleanup #1997 .
2024-06-24 09:03:24 +02:00
5aad0d6aca
Merge pull request #1997 from FlyGoat/axi-id-fixes
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integration/soc: data_width_convert: Inherit more bus properties
2024-06-24 09:00:31 +02:00
a0763bf652
liblitespi: fix xor-used-as-pow bug
2024-06-24 16:37:36 +10:00
af3d2a29fc
csr_bus: Honour re signal from the upstream bus
...
Currently CSR bus assumed that ~we means reading, that created
a problem that when for a CSR if reading has side effects and adr
parked unintentionally at that CSR, the reading side effect will be
triggered.
For SoCs, this happened when upstream bus issued a write transaction
with wishbone.sel, then on CSR bus it will be translated
as adr = addr, we = 0, which will be interpreted as a read to such
address, and trigger undesired side effect for such CSR.
Such upstream transaction will be generated by our bus width converter.
Given that we signal already presents in CSR Interface, the easiest way
to handle such situation is to generate re signal at bus bridges and
propagate it all the way down to the Interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 19:35:19 +01:00
9bdc22adfb
soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
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Don't do bus_addressing_convert as it's being handled in AHB2Wishbone
logic.
Add addressing parameters for AHBInterface constructor as required
by soc code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 16:18:26 +01:00
22f9c063db
Merge pull request #1949 from alexey-morozov/master
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The case when AWVALID and WVALID are not asserted at the same cycle
2024-06-23 09:03:17 +02:00
3d530e0b59
integration/soc: data_width_convert: Inherit more bus properties
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For data_width converter we need to ensure that adapted interface
have same properties as it's parent interface, so that id and user
signals for AXI will be propagated properly from parent to adapted
interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-22 17:54:41 +01:00
dd01a87653
Merge pull request #1993 from FlyGoat/jtag-patch
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Expand litex_sim JTAG support to more CPUs
2024-06-22 14:34:50 +02:00
0559f3f033
core: add watchdog feature
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Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-21 17:13:03 +02:00
29bdf6805f
Merge pull request #1840 from motec-research/parser_set_defaults_improvements
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Parser set defaults improvements
2024-06-21 10:52:09 +02:00
f40f63ae29
Merge pull request #1995 from VOGL-electronic/soc_spi_master_int
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soc: add_spi_master: make spi_clk_freq an int
2024-06-19 19:34:31 +02:00
447469b0aa
soc: add_spi_master: make spi_clk_freq an int
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convert spi_clk_freq to an int. this way the constant is also an int.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-19 16:29:35 +02:00
d9854582c6
build/lattice/radiant: allows extra configuration (prj_set_strategy_value XX=YY) to be added at script creation time
2024-06-19 16:22:30 +02:00
d6b0c84f9c
Merge pull request #1992 from motec-research/fix_MockCSRRegion_base
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integration/export: Fix MockCSRRegion base definition.
2024-06-19 09:13:49 +02:00
e6353c8898
Merge pull request #1991 from motec-research/add_json_excludes
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Add json excludes
2024-06-19 09:12:22 +02:00
146617eae8
soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default
2024-06-18 22:14:24 +02:00
cc21c662ca
soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default
2024-06-18 19:46:56 +02:00
50c8ef07b6
jtagremote: Implement ntrst pin
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ntrst pin is critical to some JTAG taps to put tap
into a known state.
Implement it in jtagremote testbench with corresponding
remote bitbang commands and hook it up in litex_sim.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-18 14:49:43 +01:00
f46ef03f42
build/openfpgaloader: print command before executing it to ease debugging/manual tests.
2024-06-18 15:35:27 +02:00
a8b3f36592
soc/cores/cpu: Implement add_jtag method
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Implement add_jtag method for naxriscv, vexiiriscv and vexriscv_smp,
which is the de facto way to add JTAG ports to pads on other CPUs.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-18 14:14:52 +01:00
63d72a87e6
soc/cores/cpu/zynqmp/core.py: added CAN over EMIO support
2024-06-18 12:26:36 +02:00
0d1d378966
soc/cores/cpu/zynqmp/core.py: added interrupts support
2024-06-18 10:59:42 +02:00
0f7ea96812
build/parser: detect invalid defaults
2024-06-18 09:37:31 +10:00
4730ee2288
build/parser: support set_default(cpu_type="xxx")
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Ensures args_fill() for new cpu_type is called, allowing for patterns
in a target file like:
parser.set_defaults(cpu_type="vexriscv_smp")
parser.set_defaults(cpu_variant="linux")
parser.set_defaults(with_fpu=True)
2024-06-18 09:37:31 +10:00
dad04eedef
integration/export: Fix MockCSRRegion base definition.
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MockCSR are not related to csr_base
2024-06-18 09:07:39 +10:00
56c284e9bc
soc/integraion/builder: exclude some constants in add_json()
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Interrupt numbers from a downstream soc are not relevant in the main SOC
so exclude them by default.
2024-06-18 09:01:28 +10:00
702761d789
soc/integraion/builder: fix variable names
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In _get_json_*() variable names were transposed in two places
resulting in confusing code with correct functionality.
2024-06-18 09:01:28 +10:00
485341a1cf
soc/cores/cpu/zynq7000/core.py: fix missing CAN IO mode (security/nitpick)
2024-06-17 18:26:28 +02:00
fba7ce42ec
soc/cores/cpu/zynq7000/core.py: PS CANx support with EMIO pads
2024-06-17 18:09:00 +02:00
6c4a756655
soc/cores/cpu/zynq7000/core.py: added GPx tcl configuration
2024-06-17 17:18:24 +02:00
1335d3cebc
soc/cores/cpu/zynq7000/core.py: enable F2P interrupts
2024-06-17 16:35:26 +02:00
45928a3ce1
soc/cores/cpu/zynq7000/core.py: delayed filling ps7_tcl with config at finalize time
2024-06-17 16:29:23 +02:00
3f095a260d
Fix HP slave clock source and specify AXI version
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The absence of WID signal in AXI4 when compared to AXI3 can sometimes cause problems.
2024-06-17 16:16:07 +02:00
a899c23f65
soc/interconnect/packet: Add default values for HeaderField parameters.
2024-06-17 10:54:53 +02:00
81b70d1e37
soc/integration/builder: Only generate svd/memory.x export when specified (Since often not required and generation does not seems robust to all designs).
2024-06-14 14:58:06 +02:00
69008d7d5e
software/libbase/isr.c: Fix regression.
2024-06-14 14:08:22 +02:00
8278ff6622
software/libbase/isr.c: Generalize irq_table/attach/detach to all CPUS to have a common approach.
2024-06-14 12:08:52 +02:00
45753a3cc2
software/libbase/isr.c: Move ISR handling in more logical order (RISC-V PLIC first).
2024-06-14 11:49:33 +02:00
38e060c354
software/libbase/isr.c: Cleanup code a bit.
2024-06-14 11:47:06 +02:00
6164a55c6b
cpu/cva6: Switch to common PLIC handling code to make it similar to other PLIC based CPU and avoid code "duplication".
2024-06-14 11:26:43 +02:00
b58186a99d
build/vhd2v_converter: Add GHDL synth woraround.
2024-06-14 11:25:21 +02:00
28d4aff10f
vexii non coherent config write bandwidth improvment
2024-06-13 23:20:25 +02:00
3fa3532f16
cores/video: Add fifo_depth parameter to add_video_framebuffer and use new KILOBYTE to define depth.
2024-06-13 12:59:09 +02:00
491974c719
litex_json2dts_linux: Cleanup bootargs IP address generation.
2024-06-13 12:14:44 +02:00
02d6e9760a
litex_json2dts_linux: Improve/rework RISC-V cpu_isa_base/cpu_isa_extentions and make it specific to RISC-V CPUs.
2024-06-13 11:55:54 +02:00
fcf9b3b335
litex_json2dts_linux: Use new byte size definition from litex.gen.common.
2024-06-13 09:55:19 +02:00
d782a0f8c6
litex/gen/common: Add short and long byte size definitions.
2024-06-13 09:54:20 +02:00
abdf6d3ee7
soc/integration: Generate CPU_FAMILY config and use it to simplify litex_json2dts_linux.py.
2024-06-13 09:33:04 +02:00
962bd67431
litex_json2dts_linux: Rename ncpus to cpu_count (Consistency with other variables).
2024-06-13 09:12:41 +02:00
2ddf9bb4e5
Merge pull request #1985 from VOGL-electronic/add_spi_master
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soc.py: Add spi master and changes in litex_json2dts_zephyr.py for the spi drivers
2024-06-13 09:01:48 +02:00
7306c3862e
Merge pull request #1984 from VOGL-electronic/json2renode_elf
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litex_json2renode.py: add option for elf bios file and correct vexriscv variants
2024-06-13 09:00:25 +02:00
2e4813d6ae
Fix vexii axi3
2024-06-12 19:33:20 +02:00
eb3aca2a46
build/vhd2v_converter: Make instance rename when multiple instance more robust.
2024-06-12 15:16:03 +02:00
8d8dd117b6
soc/integration/builder: Now generates exports by default to output_dir with default name unless explicitly specified.
2024-06-12 11:44:34 +02:00
8bb10e1617
cpu/vexii: Add AXI3 support via --with-axi3
2024-06-12 11:25:18 +02:00
6ed61e11bc
Merge pull request #1983 from Dolu1990/vexiiriscv
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linux dts: add vexii clint support
2024-06-11 18:40:13 +02:00
8c80a6c19c
linux dts: rework "rocket" in cpu_name into cpu_name == "rocket"
2024-06-11 13:08:25 +02:00
bb155b5a90
litex_json2dts_zephyr.py: add custon handler for spiflash
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add custon handler for spiflash.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-11 11:10:57 +02:00
44b6fb5a28
add spi master function
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add spi master function and dts wrapper for zephyr.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-11 11:10:57 +02:00
53ae12ca65
litex_json2renode: correct VexRiscv variants
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corrrect the VexRiscv variants.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-11 10:42:36 +02:00
1ee2e3a31d
litex_json2renode: add option for elf bios
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add option for elf bios file.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-11 10:41:26 +02:00
87ae5db16b
linux dts: add vexii clint support
2024-06-10 18:10:13 +02:00
f0b0d8db29
linux dts: add vexii clint support
2024-06-10 17:02:00 +02:00
7f81499cc5
Merge pull request #1923 from Dolu1990/vexiiriscv
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cpu/vexiiriscv integration
2024-06-08 15:37:37 +02:00
9c202b59d1
Fix axi id width
2024-06-07 18:33:05 +02:00
bd96b47041
Vexii fix mem data width
2024-06-06 16:36:56 +02:00
e25de0f499
build/vhd2v_converter.py: pass work_package to platform
2024-06-06 15:24:20 +02:00
0e04949485
vexii fix l1 cache size
2024-06-06 13:50:27 +02:00
abcc0b8ab6
Fix EOS-S3 build on F4PGA
2024-05-31 12:23:19 +02:00
329bd36f7f
tools/litex_json2dts_linux: Update.
2024-05-30 12:07:54 +02:00
cc1a37e386
soc/intergration: Define platform/identifier as configs (and change PLATFORM to PLATFORM_NAME).
2024-05-30 09:28:34 +02:00
72854b8bef
soc/integration/soc: Move adding constant for identifier directly to add_identifier method.
2024-05-30 09:19:24 +02:00
Dolu1990
Florent Kermarrec
Andrew Dennison
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Pepijn de Vos
Fin Maaß
Mai-Lapyst
Mai-Lapyst
Matthias Breithaupt
Richard Tucker
inc
Jiaxun Yang
JoyBed
Artur Kowalski