e9a4b178ce
build: efinix: platform.py: add `get_pins_location` and `get_pins_name`
...
add `get_pins_location` and `get_pins_name`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
f8dc03810d
build: efinix: use LiteXContext to get platform
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use LiteXContext to get platform.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:41 +02:00
afcc477c4e
efinix: common: replace `is_inclk_inverted`
...
replace `is_inclk_inverted` with `in_clk_inv` and `out_clk_inv`.
This way thwe right prop is set in the ifacewriter.py.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:11:39 +02:00
a605e75873
efinix: ifacewriter: remove deprecated GPIO properties
...
removes `OE_CLK_PIN_INV` and `OE_CLK_PIN` as they
got deprecated in efinity 2023.1.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
2c3536720c
efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block
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add `in_clk_inv` for GPIO INPUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
10ab1b76c0
efinix: ifacewriter: fix `out_reg` in GPIO INOUT block
...
fix `out_reg` in GPIO INOUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
b135f71512
build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.
2024-09-26 12:58:54 +02:00
b5e91473b7
build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.
2024-09-26 11:50:37 +02:00
0e337e2079
Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input
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build: efinix: common.py; add `SDRInput`
2024-09-26 11:43:20 +02:00
a19fbb70c4
Merge pull request #2078 from VOGL-electronic/efinix_add_ipm
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build: efinix: add function to add ip
2024-09-26 11:42:34 +02:00
b11cc8c3eb
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
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Efinix iface signal names.
2024-09-26 11:42:02 +02:00
39d292a3c7
build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.
2024-09-26 10:38:05 +02:00
a3a55fc8fb
build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.
2024-09-26 10:14:42 +02:00
fde9d2e4ad
build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
...
Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.
2024-09-26 10:13:58 +02:00
61f715e6e7
build: efinix: common.py; add `SDRInput`
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add `SDRInput` for efinix
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:17:53 +02:00
c3e87367c3
soc/cores/vexriscv_smp: Add the generation of the default sim config ( https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405 )
2024-09-25 10:38:37 +02:00
b86d76baed
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.
2024-09-25 08:56:51 +02:00
8a6264c4f6
build: efinix: add function to add ip
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add function to add efinix IP.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-24 11:59:28 +02:00
c95a6e041c
soc/interconnect/stream: Add Delay module.
2024-09-23 12:23:29 +02:00
baff4c69fe
Merge pull request #2075 from trabucayre/efinix_clkinput_signal
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build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 11:59:06 +02:00
033ec13f08
Merge pull request #2076 from trabucayre/xc7s_jtag
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Spartan7 jtag support
2024-09-19 11:53:55 +02:00
6e9dffdbf5
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado).
2024-09-19 11:10:51 +02:00
ad2c3fcea7
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant.
2024-09-19 09:21:13 +02:00
f1e1f3530e
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)
2024-09-19 09:14:30 +02:00
aca959b059
build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 09:12:36 +02:00
e072156b93
build/xilinx/platform.py: added xc7s to the list of device supporting jtag access
2024-09-19 06:49:44 +02:00
fc68f031a1
soc/cores/jtag.py: added Spartan7 definition for BSCANE2
2024-09-19 06:49:10 +02:00
9bacbe130b
Merge pull request #1974 from motec-research/dts_zephyr_updates
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DTS zephyr updates
2024-09-17 14:58:51 +02:00
a350d2e909
soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux.
2024-09-13 19:21:26 +02:00
2a19a61e05
build/xilinx/vivado: Fix typo.
2024-09-13 10:39:13 +02:00
99550809b3
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet
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sim: add HW_PREAMBLE_CRC for ethernet
2024-09-13 08:36:40 +02:00
dc8c1bd9cd
build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives.
2024-09-12 18:04:25 +02:00
203c9816b2
integration/soc/add_etherbone: Allow 64-bit support now that validated.
2024-09-12 13:39:13 +02:00
2fd8c2cd61
sim: add HW_PREAMBLE_CRC for ethernet
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This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble
is automatically attached by the tap, there is no need to add it from
the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-09-12 10:07:43 +02:00
b41a526e81
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac
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soc.py: add_ethernet: add mac addr constant
2024-09-11 11:54:14 +02:00
11c7b69fd4
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix
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bios: boot.c: fix warnings
2024-09-11 11:53:52 +02:00
7b3f1509d1
soc.py: add_ethernet: add mac addr constant
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add mac addr constant to add_ethernet,
so it matches the one from add_etherbone.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:21:53 +02:00
3966e3438c
bios: boot.c: fix warnings
...
this fixes the warnings, when compiling.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:15:56 +02:00
dc8b74cc58
Merge pull request #2060 from Dolu1990/efinix-rework
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build/efinix: add a few IO primitives, IO constraints, sdc rework
2024-09-10 18:40:10 +02:00
a80f290d80
soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name
2024-09-10 18:07:34 +02:00
ad09ffc150
soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str
2024-09-10 18:03:12 +02:00
109ae17e9e
build/efinix/common.py: replaced i as str by a ClockDomain
2024-09-10 17:56:49 +02:00
458e0057f2
soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.
2024-09-09 18:24:14 +02:00
5cd1a57080
soc/interconnect/wishbone: Cosmetic cleanup on Cache.
2024-09-09 18:16:40 +02:00
e06045c576
Merge pull request #2059 from Dolu1990/vexii-clk-video
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soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-09 14:12:50 +02:00
2db93c8e78
core/vexiiriscv: improve l2 timings
2024-09-06 16:07:05 +02:00
bd03c496a1
bios: add spiram
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add spiram in bios, so it can enable QPI.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-05 16:31:32 +02:00
599c6dde37
litex/build/efinix/common.py add EfinixDDRTristate binding
...
Co-authored-by: Fin Maaß <info@finmaass.de>
2024-09-05 16:12:32 +02:00
c0fddb6561
build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled
2024-09-05 15:21:12 +02:00
642cfbe9a7
soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-05 15:16:15 +02:00
e62d84b77b
Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support"
...
This reverts commit 0ea6dd91aafa47c62b6d
2024-09-05 15:15:49 +02:00
0ea6dd91aa
soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-05 15:14:46 +02:00
f512c65077
vexiiriscv git update
2024-09-05 13:17:22 +02:00
2190ca403a
core/usb_ohci: fix SDRTristate clock
2024-09-05 10:24:45 +02:00
f67b39739e
soc/integration/add_ethernet: Expose full_memory_we parameter.
2024-09-05 10:18:12 +02:00
1f2418de3b
core/usb_ohci: fix SDRTristate clock
2024-09-05 10:17:22 +02:00
84e7e816c7
efinix: pll now force the generated clock into cd.clk *WARNING*
2024-09-05 10:16:43 +02:00
d3161ad74c
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-09-04 14:42:45 +02:00
d0215001f4
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
2024-09-03 17:47:40 +02:00
a90ab9dcca
efinix: Merge pt.sdc to the litex sdc to get constraints right
2024-09-03 12:05:26 +02:00
4152d22065
Revert "build/efinix/platform: fix get_pin_name()"
...
This reverts commit 0cb101da25
2024-09-03 10:24:38 +02:00
3de5832b9c
vexiiriscv: Now use pll.locked for debug reset
2024-09-03 07:58:24 +02:00
19b3f24d9f
efinix: ifacewriter support drive strength and slew
2024-09-03 07:57:30 +02:00
e01ce6f948
efinix: ifacewriter support drive strength and slew
2024-09-03 07:55:25 +02:00
babe233407
build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software)
2024-09-01 09:55:01 +02:00
3da470048a
build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model
2024-09-01 09:53:24 +02:00
2f2b292e06
vexii add with-cpu-clk
2024-08-30 18:16:56 +02:00
15cd556750
Merge pull request #2053 from enjoy-digital/hyperram_new
...
soc/cores/hyperbus: Full rewrite of HyperRAM core.
2024-08-30 15:38:59 +02:00
61b54aa491
soc/integration/soc: Fix add_peripheral.
2024-08-30 12:08:00 +02:00
c554752e8a
soc/cores/hyperbus: Add automatic read burst detection.
2024-08-30 11:53:14 +02:00
c14f1d0816
vexiiriscv add video support
2024-08-30 10:44:36 +02:00
5fb873d209
efinix: Add support for more IO
2024-08-30 10:44:10 +02:00
3bde3e9848
soc/cores/hyperbus: Add automatic write burst detection.
2024-08-29 19:20:23 +02:00
fac80c3a51
soc/cores/hyperbus: Full rewrite of HyperRAM core.
...
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.
This rewrite provides a base for future development.
2024-08-29 12:54:09 +02:00
cc3f13670a
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
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efinix: Fix PLL with external clock input ifacewriter
2024-08-28 20:13:03 +02:00
d4003b8cfa
efinix add SCHMITT_TRIGGER support
2024-08-28 19:59:30 +02:00
4ded509444
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
...
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:50:04 +02:00
6d46a5ba05
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:02:58 +02:00
0fcc27f58f
build/colognechip/colognechip.py: simplify constrains file with the new toolchain
2024-08-24 12:20:58 +02:00
07e11858c6
soc/cores/clock/colognechip.py: rework/fix locked signal
2024-08-24 12:19:34 +02:00
ef775e0b8e
Merge pull request #2043 from pepijndevos/moreapicula
...
fixes for apicula support
2024-08-24 10:37:17 +02:00
4400fbb966
Apicula: add GWINR-18 aliases
2024-08-22 16:02:41 +02:00
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
2024-08-21 17:10:36 +02:00
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
2024-08-21 15:35:21 +02:00
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
2024-08-21 12:07:55 +02:00
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
2024-08-21 11:50:46 +02:00
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
2024-08-21 11:41:13 +02:00
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
2024-08-21 11:17:55 +02:00
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
2024-08-21 10:57:36 +02:00
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
...
Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
2024-08-20 14:58:51 +02:00
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
2024-08-20 14:44:33 +02:00
bfe000150c
soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.
2024-08-20 14:25:23 +02:00
7b413352c2
soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
2024-08-20 12:04:23 +02:00
8f5c2dfbca
soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).
2024-08-20 12:03:40 +02:00
3a53a92bb2
soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.
2024-08-20 11:38:33 +02:00
9c1958d692
soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.
2024-08-20 11:26:58 +02:00
c1403db407
json2dts_zephyr: omit disable handler
...
omit disable handler for the sdcard peripherals,
as they still don't have a driver in zephyr and are not in the board dts.
This way the build in zephyr will not fail.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-20 11:23:21 +02:00
db86ec08b8
soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
2024-08-20 11:12:17 +02:00
1f71f3d68b
soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
2024-08-20 10:40:24 +02:00
a960dc33bc
soc/cores/hyperbus: Minor cleanup changes.
2024-08-20 10:26:34 +02:00
b95b66b554
soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).
2024-08-20 10:10:53 +02:00
c5416f1680
fixes for apicula support
2024-08-19 19:54:26 +02:00
afc66fd5cf
cores/picorv32: Fix idbus.sel for reads.
2024-08-19 13:34:50 +02:00
6623a5b691
Merge pull request #2028 from VOGL-electronic/spi_ram_add
...
soc: add add_spi_ram function
2024-08-16 19:08:48 +02:00
039be2a248
add dual use gpio options
2024-08-16 15:56:24 +02:00
dc3f2d6421
Add missing license header to apicula.py
2024-08-15 01:54:31 +02:00
623536cd6a
Remove empty build_timing_constraints override in GowinApiculaToolchain
2024-08-15 01:52:22 +02:00
e0968b3574
Adds apicula toolchain to gowin platform
2024-08-12 06:55:11 +02:00
3d0fe4ebca
Fix litex.build.gowin's __init__.py; closes #2034
2024-08-11 05:44:14 +02:00
3cd820974a
build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)
2024-08-04 09:39:46 +02:00
cd457c9809
soc: add l2 cache to spi_ram
...
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
e29dc39377
openocd/jtagspi: Allow users to specify additional init commands
...
This change makes it possible to e.g. use flahs chips that would not be correctly detected by OpenOCD.
All that has to be done is to add `init_commands=["jtagspi set 0 \"name\" {size} {pagesize} {read_cmd} 0 {pprg_cmd} {mass_erase_cmd} {sector_size} {sector_erase_cmd}"]`.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
41b346d141
bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)
...
Instead of reading each individual byte, causing multiple 4-byte requests to each address, this
change results in a single read for each address.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
03a0a6fd9b
soc: add add_spi_ram function
...
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
1f6673c6eb
build/altera/common.py: implement SDRTristate for Agilex5 family
2024-07-30 16:36:05 +02:00
e19dfa8800
tools/litex_json2dts_zephyr: fix reg format
...
addr size pairs should be enclosed '< >' and comma separated to be
dts compliant.
2024-07-29 09:16:59 +10:00
2776b63d1a
tools/litex_json2dts_zephyr: improve indentation
...
To support linux dts generation.
2024-07-29 09:16:59 +10:00
3041150773
Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special
...
build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-26 18:26:19 +02:00
ba8830e6cd
global: Remove @trabucayre's tracers :)
2024-07-26 12:57:01 +02:00
5c5bc82f22
interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.
...
Needs to be filtered on param_fifo.sink.ready and not payload_fifo.sink.ready.
2024-07-26 11:52:17 +02:00
dc04949d78
build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-25 14:11:06 +02:00
c51d22074f
soc/integration/soc/add_uart: Allow directly passing uart_pads.
...
Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
2024-07-22 16:23:22 +02:00
b8cb6da2b9
soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output
2024-07-22 15:11:40 +02:00
ecd0f0e548
cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.
2024-07-22 14:24:34 +02:00
4662b95f16
Merge pull request #2012 from machdyne/master
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soc/cores/video: Add additional color formats
2024-07-21 09:34:00 +02:00
f99658200e
soc/cores/i2c: rewrite state machine
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* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
2024-07-20 15:45:44 +10:00
dce152b348
soc/cores/i2c: change SDA 1 or 2 cycles earlier
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* update 'only change SDA when SCL is stable' to max 1 sys_clk delay
2024-07-20 15:45:44 +10:00
e36946b251
soc/cores/i2c: convert to LiteXModule and name some components
2024-07-20 15:45:44 +10:00
c867d5647b
soc/cores/i2c: only change SDA when SCL is stable
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Avoid changing SDA immediately in states WRITE0 and READ0 to guarantee SDA hold is > 0
2024-07-20 15:45:44 +10:00
aef6cb3103
soc/cores/i2c: remove unnecessary code
2024-07-20 15:45:44 +10:00
5504cc626f
soc/cores/i2c: change ISR to rising edge of idle
2024-07-20 15:45:44 +10:00
b8b6ecef7c
soc/cores/i2c: fix CSR generation
2024-07-20 15:45:44 +10:00
ad37e17743
soc/cores/i2c: add interrupt
2024-07-20 15:45:44 +10:00
a079da922a
soc/cores: adapt misoc i2c to litex
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Also add misoc license information.
2024-07-20 15:45:44 +10:00
9dc3eefb7d
soc/cores/i2c: import from misoc
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* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
2024-07-20 15:45:44 +10:00
a014c4f07c
tools/litex_sim: Cleanup imports.
2024-07-18 12:16:23 +02:00
cbe7413fee
Fix VexiiRiscv
2024-07-18 11:32:07 +02:00
f687425cb1
Update VexiiRiscv
2024-07-18 11:26:13 +02:00
9fa1b4c123
Update Nax/Vexii
2024-07-12 16:17:30 +02:00
aef5a2094e
soc/cores/video: Add additional color formats
2024-07-10 15:21:51 +02:00
22ff3ac42d
Merge branch 'master' into vexiiriscv
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# Conflicts:
# litex/soc/cores/cpu/vexiiriscv/core.py
2024-07-10 09:37:43 +02:00
1267ba8ae6
Update Nax/Vexii
2024-07-10 09:35:34 +02:00
e4e9bd2125
interconnect/axi/axi_lite: Add bursting property even if always False.
2024-07-09 17:02:54 +02:00
Fin Maaß
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
Matthias Breithaupt
Andrew Dennison
Gwenhael Goavec-Merou
Pepijn de Vos
Mai-Lapyst
Mai-Lapyst
Richard Tucker
inc