0a5883901a
soc: integrate constants/build
2020-02-08 22:08:37 +01:00
014d5a56a8
soc: show sorted regions (by origin) / locs
2020-02-08 21:34:26 +01:00
c69b6b7c12
soc: simplify color theme
2020-02-08 21:30:34 +01:00
3cb90297ac
soc: add add_uart method
2020-02-08 10:19:18 +01:00
e5cacb8bbd
soc_core: cleanup imports
2020-02-07 23:16:29 +01:00
33d498b826
soc_core: get_csr_address no longer used
2020-02-07 23:11:08 +01:00
1feff1d7d5
soc: integrate CSR master/interconnect/collection and IRQ collection
2020-02-07 19:50:35 +01:00
3ba7c29ed9
soc: add add_constant/add_config methods
2020-02-07 19:09:54 +01:00
29bbe4c02a
soc: add add_csr_bridge method
2020-02-07 18:49:20 +01:00
b84c291c34
soc: add add_controller/add_identifier/add_timer methods
2020-02-07 18:31:50 +01:00
9445c33e9d
soc: add add_ram/add_rom methods
2020-02-07 16:06:32 +01:00
e5a8ac1dab
soc: add automatic bus data width convertion to add_master/add_slave
2020-02-07 15:31:59 +01:00
8f67f1157d
soc/soc_core: cleanup, remove some unused attributes
2020-02-07 15:19:02 +01:00
2c6e5066a7
soc: move SoCController from soc_core to soc
2020-02-07 14:52:53 +01:00
848fa20d1e
soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler
2020-02-07 13:25:54 +01:00
39458c92eb
soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined
2020-02-06 19:50:44 +01:00
1eff0799a4
soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined
2020-02-06 18:50:17 +01:00
8bc420679a
soc/integration: initial adaptation to new SoC class
2020-02-06 18:21:13 +01:00
6baa07a69b
soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC
2020-02-06 11:06:41 +01:00
9b11e9192d
cpu/vexriscv: update submodule
2020-02-06 10:50:35 +01:00
ae085782ae
doc: add lxsocdoc.md (README from lxsocdoc repository)
2020-02-05 11:06:57 +01:00
5ff02e23a0
Merge pull request #375 from xobs/add-lxsocdoc
...
Add lxsocdoc
2020-02-05 10:15:21 +01:00
1944d8d9d0
bios/main: add LiteX tagline
2020-02-04 19:14:23 +01:00
40cddca933
Merge pull request #376 from antmicro/build-sim-do-not-override-C-LD-FLAGS
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build/sim: allow to use environment's {C,LD}FLAGS
2020-02-04 18:19:33 +01:00
90fe585003
build/sim: allow to use environment's {C,LD}FLAGS
...
There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
2020-02-04 17:31:31 +01:00
58598d4fda
integration: svd: move svd generation to `export`
...
It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h. This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 23:49:08 +08:00
73ed7e564c
soc: doc: use sphinx toctree as it was intended
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The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely. This patch causes it to be used correctly,
which removes the need for double-including various sections.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:34:10 +08:00
7c3bc0b09f
litex-doc: initial merge of lxsocdoc
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lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.
This merges the existing lxsocdoc distribution into the `soc/doc` directory.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:14:41 +08:00
bd6fd3da55
Merge pull request #373 from antmicro/l2-reverse
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tools/litex_sim: use l2_reverse flag
2020-02-03 12:55:48 +01:00
f3b068e2ee
tools/litex_sim: use l2_reverse flag
2020-02-03 12:03:57 +01:00
3350d33f9c
wishbone/Cache: add reverse parameter
2020-01-31 19:31:33 +01:00
eff9caee6a
soc_sdram: add l2_reverse parameter
2020-01-31 19:18:07 +01:00
6e5b47f4c6
Merge pull request #370 from Disasm/fixes
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Small fixes
2020-01-31 18:27:26 +01:00
de88ed282a
Fix argument descriptions
2020-01-31 18:54:25 +03:00
eb49ec217e
Pass --csr-json to the Builder
2020-01-31 18:53:50 +03:00
b69f2993e4
soc_core: add UART bridge support (simplify having to do it externally)
2020-01-31 15:12:18 +01:00
7a6c04db9e
build/altera/quartus: fix fmt_r typo
2020-01-30 13:55:13 +01:00
c6b9676db8
cpu/minerva: update (use new nMigen API)
2020-01-30 13:42:02 +01:00
9d2894727e
inteconnect/stream: use PipeValid implementation for Buffer
2020-01-30 09:36:04 +01:00
1c88c0f896
inteconnect/stream: cleanup
2020-01-30 09:32:04 +01:00
cafd9c358a
Merge pull request #366 from gsomlo/gls-csr-followup
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software, integration/export: (re-)expose CSR subregister accessors
2020-01-30 08:18:12 +01:00
ff2775c264
software, integration/export: (re-)expose CSR subregister accessors
...
Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.
This restores downstream ability to override CSR handling at the
subregister accessor level.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-29 14:29:24 -05:00
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
b22ad1acfb
build/xilinx/vivado: improve readability of generated tcl/xdc files
2020-01-29 16:27:18 +01:00
7bc34a9bc7
integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).
...
When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
2020-01-29 08:31:41 +01:00
b4b56db4e3
Merge pull request #363 from antmicro/litex-sim-ddr4
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tools/litex_sim: add ddr4 PhySettings
2020-01-28 15:36:24 +01:00
c02dd5e8f9
tools/litex_sim: add ddr4 PhySettings
2020-01-28 14:28:24 +01:00
0820adbda1
tools/litex_sim: add --sdram-init parameter
2020-01-27 21:30:13 +01:00
01ae10b803
software/bios: revert M-Labs MiSoC copyright.
2020-01-27 13:12:37 +01:00
ea5ef8c1be
README: update copyright year and make sure LICENSE/README both mention MiSoC
2020-01-27 12:15:11 +01:00
Florent Kermarrec
Sean Cross
Mariusz Glebocki
Piotr Binkowski
Vadim Kaushan
Gabriel Somlo