Sebastien Bourdeauducq
|
72ef4b9683
|
ioo+pytholite: use new Module API
|
2013-04-10 23:42:46 +02:00 |
|
Sebastien Bourdeauducq
|
746acdacd1
|
ioo: move to genlib
|
2013-04-10 22:28:53 +02:00 |
|
Sebastien Bourdeauducq
|
692794a21f
|
flow: use Module and new Record APIs
|
2013-04-10 19:12:42 +02:00 |
|
Sebastien Bourdeauducq
|
6a3c413717
|
New bidirectional-capable Record API
|
2013-04-01 21:53:33 +02:00 |
|
Sebastien Bourdeauducq
|
c4f4143591
|
New CSR API
|
2013-03-30 17:28:41 +01:00 |
|
Sebastien Bourdeauducq
|
b38818eb17
|
examples/sim/fir: convert to new API
|
2013-03-19 11:46:27 +01:00 |
|
Sebastien Bourdeauducq
|
af4eb02551
|
examples/basic/arrays: demonstrate lowering of Array in Instance expression
|
2013-03-18 18:37:23 +01:00 |
|
Sebastien Bourdeauducq
|
e2d156ef64
|
genlib/cdc/MultiReg: remove idomain
|
2013-03-15 19:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
51bec340ab
|
sim: remove PureSimulable (superseded by Module)
|
2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
208e039bbb
|
Local clock domain example
|
2013-03-15 18:18:32 +01:00 |
|
Sebastien Bourdeauducq
|
c99cc9343f
|
examples/pytholite: use new APIs
|
2013-03-12 16:59:24 +01:00 |
|
Sebastien Bourdeauducq
|
907bfa87f4
|
examples/basic: use new APIs
|
2013-03-12 16:45:28 +01:00 |
|
Sebastien Bourdeauducq
|
c2d54f481f
|
examples/psync: cleanup
|
2013-02-23 19:14:31 +01:00 |
|
Sebastien Bourdeauducq
|
6abac5907b
|
examples/basic/psync: demonstrate the new features
|
2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
92b67df41c
|
sim: default runner to Icarus Verilog
|
2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
314a6c7743
|
corelogic: complex arithmetic support
|
2013-01-05 14:18:36 +01:00 |
|
Sebastien Bourdeauducq
|
4d0db2cb05
|
examples/pytholite: fix imports
|
2012-12-16 20:26:23 +01:00 |
|
Sebastien Bourdeauducq
|
a67f483f0f
|
Token: support idle_wait
|
2012-12-14 19:16:22 +01:00 |
|
Sebastien Bourdeauducq
|
6f99241585
|
Move Token to migen.flow.transactions
|
2012-12-14 15:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
a7227d7d2b
|
Remove ActorNode
|
2012-12-12 22:20:48 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
2a3ef28041
|
examples/sim/dataflow: update to new APIs
|
2012-11-28 22:44:14 +01:00 |
|
Sebastien Bourdeauducq
|
39d577d65e
|
examples/dataflow/dma: update to new APIs
|
2012-11-28 22:42:01 +01:00 |
|
Sebastien Bourdeauducq
|
7c4b5931bc
|
examples/basic: remove unroll example
|
2012-11-28 22:16:02 +01:00 |
|
Sebastien Bourdeauducq
|
5440fa715c
|
examples/basic/arrays: add array assignment to fragment
|
2012-11-26 22:47:35 +01:00 |
|
Sebastien Bourdeauducq
|
2418367c7a
|
examples/sim/memory: do not use MemoryPort
|
2012-11-26 18:19:10 +01:00 |
|
Sebastien Bourdeauducq
|
dac0d11e52
|
actorlib/sim: Dumper
|
2012-11-24 00:00:07 +01:00 |
|
Sebastien Bourdeauducq
|
784a399431
|
examples/memory: use new get_port API
|
2012-11-23 19:18:08 +01:00 |
|
Sebastien Bourdeauducq
|
7c6ebcf753
|
examples/pytholite/uio: demonstrate memories
|
2012-11-23 16:24:20 +01:00 |
|
Sebastien Bourdeauducq
|
20d87682ad
|
examples/pytholite/uio: simulate and convert Pytholite
|
2012-11-23 13:10:40 +01:00 |
|
Sebastien Bourdeauducq
|
89643bc434
|
sim/ipc/Message: convert values
|
2012-11-17 23:19:40 +01:00 |
|
Sebastien Bourdeauducq
|
6434ddd95a
|
examples/pytholite: add uio example
|
2012-11-17 22:26:14 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
|
bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
748741b49a
|
examples/pytholite/basic: demonstrate conversion to Verilog
|
2012-11-16 19:38:57 +01:00 |
|
Sebastien Bourdeauducq
|
7c7addbbe8
|
examples: basic Pytholite demo
|
2012-11-16 19:34:34 +01:00 |
|
Sebastien Bourdeauducq
|
daee4fb58c
|
transform/unroll_sync: autodetect in/out
|
2012-10-15 20:32:07 +02:00 |
|
Sebastien Bourdeauducq
|
eacba52fba
|
transform/unroll: support for variables
|
2012-10-12 19:54:03 +02:00 |
|
Sebastien Bourdeauducq
|
e5fc9cc675
|
transform: unroll
|
2012-10-12 13:16:39 +02:00 |
|
Sebastien Bourdeauducq
|
e410973352
|
bank: support for atomic writes
|
2012-10-08 18:43:18 +02:00 |
|
Sebastien Bourdeauducq
|
fc3187317b
|
examples: demonstrate multi-clock support
|
2012-09-10 23:46:19 +02:00 |
|
Sebastien Bourdeauducq
|
f7b1e67d08
|
examples: update LM32 instance
|
2012-09-10 23:45:27 +02:00 |
|
Sebastien Bourdeauducq
|
2a7d2908d1
|
examples: new namer
|
2012-09-09 19:34:46 +02:00 |
|
Sebastien Bourdeauducq
|
5bf19c155f
|
sim: ensure clean IPC shutdown
|
2012-08-05 00:16:11 +02:00 |
|
Sebastien Bourdeauducq
|
a55fee78d2
|
examples/dataflow/dma: test OOO ASMI reader
|
2012-07-12 19:45:12 +02:00 |
|
Sebastien Bourdeauducq
|
eed8fa374d
|
fhdl/arrays: use correct BV for intermediate signals
|
2012-07-11 12:06:32 +02:00 |
|
Sebastien Bourdeauducq
|
ed27783a53
|
fhdl: arrays (TODO: use correct BV for intermediate signals)
|
2012-07-09 15:16:38 +02:00 |
|
Sebastien Bourdeauducq
|
920aa5dc60
|
actorlib: merge composer into ala + derive ComposableSource from ActorNode
|
2012-06-25 11:34:58 +02:00 |
|
Sebastien Bourdeauducq
|
fd233d5b3c
|
Move arithmetic actors to actorlib
|
2012-06-24 19:13:49 +02:00 |
|
Sebastien Bourdeauducq
|
1edaec0d75
|
control.For -> misc.IntSequence
|
2012-06-22 15:01:47 +02:00 |
|
Sebastien Bourdeauducq
|
8142c4f0d9
|
examples/dataflow/dma: use new dataflow API (thanks Ross Manyika for reporting)
|
2012-06-22 13:58:36 +02:00 |
|
Sebastien Bourdeauducq
|
67dc911788
|
examples/sim/dataflow: use new dataflow API (thanks Ross Manyika for reporting)
|
2012-06-22 13:22:36 +02:00 |
|
Sebastien Bourdeauducq
|
956d1257c2
|
examples/dataflow/structuring: infinite source
|
2012-06-21 00:44:41 +02:00 |
|
Sebastien Bourdeauducq
|
34d8ae3c11
|
flow: perftools
|
2012-06-20 21:59:17 +02:00 |
|
Sebastien Bourdeauducq
|
9a38c47048
|
examples/dataflow/structuring: test Cast
|
2012-06-20 18:29:03 +02:00 |
|
Sebastien Bourdeauducq
|
6fac3f027f
|
examples/dataflow: structuring test
|
2012-06-20 18:25:01 +02:00 |
|
Sebastien Bourdeauducq
|
1576cb0950
|
actorlib/control: simplify + fix
|
2012-06-17 21:19:47 +02:00 |
|
Sebastien Bourdeauducq
|
e1ff776752
|
remove spurious module
|
2012-06-17 21:19:22 +02:00 |
|
Sebastien Bourdeauducq
|
4873cfe1a7
|
flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor
|
2012-06-17 13:45:18 +02:00 |
|
Sebastien Bourdeauducq
|
21eb17fc36
|
examples/flow: Fibonacci demo
|
2012-06-16 22:41:34 +02:00 |
|
Sebastien Bourdeauducq
|
f7cac15b34
|
examples/flow/arithmetic: cleanup
|
2012-06-16 22:37:25 +02:00 |
|
Sebastien Bourdeauducq
|
c1450daa93
|
flow: insert splitters
|
2012-06-16 21:23:42 +02:00 |
|
Sebastien Bourdeauducq
|
5c139511e8
|
examples/flow/arithmetic: simulate
|
2012-06-16 19:23:59 +02:00 |
|
Sebastien Bourdeauducq
|
bde8361e19
|
flow: insert combinators and infer plumbing layout
|
2012-06-16 17:30:54 +02:00 |
|
Sebastien Bourdeauducq
|
da522cd58d
|
Abstract actor graphs
|
2012-06-15 17:52:19 +02:00 |
|
Sebastien Bourdeauducq
|
b14be4c8a3
|
actorlib: ASMI sequential reader
|
2012-06-12 21:04:47 +02:00 |
|
Sebastien Bourdeauducq
|
3a58916a4f
|
examples/dataflow/dma: refactor
|
2012-06-12 19:55:57 +02:00 |
|
Sebastien Bourdeauducq
|
973c00938d
|
Reorganize examples folder
|
2012-06-12 17:49:50 +02:00 |
|
Sebastien Bourdeauducq
|
8a23451237
|
PureSimulable
|
2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
|
a591510189
|
ASMI simulation models
|
2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
|
b7a84b3750
|
wishbone: base TargetModel class
|
2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
|
ec501e7797
|
bus/wishbone: target model
|
2012-06-10 16:40:33 +02:00 |
|
Sebastien Bourdeauducq
|
5964df62db
|
examples/dataflow: only import nx when needed
|
2012-06-08 22:54:04 +02:00 |
|
Sebastien Bourdeauducq
|
009f26bb9d
|
flow/network: refactor graph
|
2012-06-08 22:49:49 +02:00 |
|
Sebastien Bourdeauducq
|
f86170e349
|
actorlib: WB writer simulation OK
|
2012-06-08 21:31:57 +02:00 |
|
Sebastien Bourdeauducq
|
356051e8a8
|
actorlib: WB reader simulation OK
|
2012-06-08 21:31:05 +02:00 |
|
Sebastien Bourdeauducq
|
910c7806cf
|
actorlib: generator-based generic simulation actor
|
2012-06-08 17:54:03 +02:00 |
|
Sebastien Bourdeauducq
|
d280723618
|
examples/fir: print Verilog source
|
2012-06-08 14:00:49 +02:00 |
|
Sebastien Bourdeauducq
|
b00e8fa826
|
examples/fir: plot input and output signals
|
2012-06-07 23:20:59 +02:00 |
|
Sebastien Bourdeauducq
|
081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
f6e76ae198
|
doc: more examples and comments
|
2012-03-10 19:38:39 +01:00 |
|
Sebastien Bourdeauducq
|
57a87b3316
|
examples: FIR filter simulation
|
2012-03-08 20:49:36 +01:00 |
|
Sebastien Bourdeauducq
|
f4adb0fe9c
|
examples: remove outdated wb_intercon simulation
|
2012-03-08 18:17:56 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
59a57e7a76
|
examples: small cleanup
|
2012-03-08 15:55:02 +01:00 |
|
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
|
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
|
Sebastien Bourdeauducq
|
6f829c7afc
|
sim: support for signed numbers
|
2012-03-06 16:46:18 +01:00 |
|
Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
|
2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |
|
Sebastien Bourdeauducq
|
aac9752558
|
sim: basic functionality working
|
2012-03-05 20:31:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
|
fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
|
ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |