Florent Kermarrec
0545d49294
liteeth/core: add with_icmp parameter
2015-07-06 21:31:20 +02:00
Florent Kermarrec
e011f9378f
use sets for leave_out
2015-07-05 22:49:23 +02:00
Florent Kermarrec
c100ef6406
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
2015-07-05 22:45:53 +02:00
Florent Kermarrec
c1ca928ec2
liteeth: small logic optimizations on mac (eases timings on spartan6)
2015-07-05 12:31:52 +02:00
Florent Kermarrec
125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
Florent Kermarrec
01c5051866
liteeth/software: fix wishbone bridge
2015-06-23 01:48:45 +02:00
Florent Kermarrec
369cf4c4d7
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
2015-06-23 01:08:49 +02:00
Florent Kermarrec
5c939b85ef
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
Florent Kermarrec
a3c0e5c4d9
liteeth/core/arp: fix missing MAC address in ARP reply
2015-06-22 23:15:00 +02:00
Florent Kermarrec
cb053dc011
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
Florent Kermarrec
d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
Florent Kermarrec
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
Florent Kermarrec
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
Florent Kermarrec
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
Florent Kermarrec
4d902b578c
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
2015-05-07 20:03:12 +02:00
Florent Kermarrec
da711ad5f1
liteusb: add simple example design with wishbone bridge and software to control it
2015-05-02 18:21:18 +02:00
Florent Kermarrec
c98bd9fd79
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
2015-05-02 17:07:58 +02:00
Florent Kermarrec
145398d874
liteeth/core/mac: minor cleanup
2015-05-02 16:48:57 +02:00
Florent Kermarrec
e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
Florent Kermarrec
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
Florent Kermarrec
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
Florent Kermarrec
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
Florent Kermarrec
a4617014f4
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00
Florent Kermarrec
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
Florent Kermarrec
5e649a6577
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
2015-05-01 20:45:04 +02:00
Florent Kermarrec
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
Florent Kermarrec
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
Florent Kermarrec
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
Florent Kermarrec
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
Florent Kermarrec
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
Florent Kermarrec
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
Florent Kermarrec
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
Florent Kermarrec
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
Florent Kermarrec
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
Florent Kermarrec
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
Florent Kermarrec
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
Florent Kermarrec
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
Florent Kermarrec
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
Florent Kermarrec
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
Florent Kermarrec
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
Florent Kermarrec
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
Florent Kermarrec
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
Florent Kermarrec
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
Florent Kermarrec
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
Florent Kermarrec
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
Florent Kermarrec
341f635a85
litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design
2015-04-18 13:58:20 +02:00
Florent Kermarrec
602eaf69c7
litepcie: fix asciiart in make.py
2015-04-17 14:10:32 +02:00
Florent Kermarrec
b4b37fb10e
litepcie: add linux driver + utilities (sysfs + dma)
2015-04-17 13:48:34 +02:00
Florent Kermarrec
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
