Sebastien Bourdeauducq
7fa1cd72a8
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
Florent Kermarrec
c0fb0ef600
fhdl/verilog: change the way we initialize reg: reg name = init_value;
...
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
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This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
Sebastien Bourdeauducq
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
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This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
2015-03-18 12:08:25 +01:00
Florent Kermarrec
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
...
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
Florent Kermarrec
e946f6e453
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
2015-03-16 23:47:07 +01:00
Sebastien Bourdeauducq
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
Florent Kermarrec
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
Sebastien Bourdeauducq
135a4fea25
fhdl/verilog: fix representation of negative integers
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Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
Robert Jordens
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
Nina Engelhardt
6f9f08f6eb
add ternary operator sel ? a : b
2013-08-12 13:15:56 +02:00
Sebastien Bourdeauducq
eb1417c5ed
fhdl: move insert_resets to tools
2013-08-08 11:32:58 +02:00
Nina Engelhardt
61b8958953
fix synthesis translate on/off switch
2013-07-26 15:55:16 +02:00
Sebastien Bourdeauducq
b7ed19c6c5
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
Sebastien Bourdeauducq
71b89e4c46
fhdl/verilog: lower complex slices before reset insertion
2013-06-30 14:32:47 +02:00
Sebastien Bourdeauducq
080afdc3f9
fhdl/verilog: fix signedness rules for comparison
2013-06-26 22:45:47 +02:00
Sebastien Bourdeauducq
b56cb3cefc
fhdl/verilog: improve error reporting
2013-06-24 19:44:25 +02:00
Sebastien Bourdeauducq
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
Florent Kermarrec
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
Sebastien Bourdeauducq
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
Sebastien Bourdeauducq
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
Sebastien Bourdeauducq
7c4e6c35e5
fhdl/verilog: support special lowering and overrides
2013-02-23 19:03:16 +01:00
Sebastien Bourdeauducq
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq
3201554f76
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
2013-01-23 15:13:06 +01:00
Sebastien Bourdeauducq
badba89686
fhdl: support nested statement lists
2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
Sebastien Bourdeauducq
261166d92b
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
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See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
Sebastien Bourdeauducq
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq
9d3e218863
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
2012-11-23 18:38:03 +01:00
Sebastien Bourdeauducq
51e2e6ecd0
fhdl/verilog: remove empty cases
2012-11-18 16:32:51 +01:00
Sebastien Bourdeauducq
c273866b08
fhdl: support expressions in instance ports
2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq
2fc9cae88a
fhdl: support inverted clock ports in instances
2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq
2e14569b5c
fhdl/verilog: sort clock domains by name
2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq
9a18a9df3f
fhdl: list signals in execution order
2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq
e16353a281
Multi-clock design support + new instance API
2012-09-10 23:45:02 +02:00
Sebastien Bourdeauducq
8de192dfbd
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq
7f47a2568a
fhdl: remove _StatementList
2012-07-13 17:07:56 +02:00
Sebastien Bourdeauducq
ed27783a53
fhdl: arrays (TODO: use correct BV for intermediate signals)
2012-07-09 15:16:38 +02:00
Sebastien Bourdeauducq
398ece8fe2
fhdl/verilog: add option to display which comb blocks are run
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This is a debug hack to help find combinatorial loops in designs.
2012-04-30 16:38:40 -05:00
Sebastien Bourdeauducq
2a4e49e381
fhdl: phase out pads
2012-04-02 19:21:43 +02:00
