29f7b94e37
bus/wishbone/sram: expose memory component
2013-11-24 23:43:14 +01:00
c5342c5b5c
bus/wishbone: style
2013-11-24 23:42:54 +01:00
99c53ed9e8
Better record layout parameterization mechanism
2013-10-23 12:54:50 +02:00
2cf6b6c768
wishbone/SRAM: fix non-32-bit bus
2013-08-26 20:32:59 +02:00
628fa8ce9e
wishbone : add DownConverter
2013-08-26 20:28:09 +02:00
6ba0d4bd0d
bus/wishbone: configurable data width
2013-07-27 22:25:07 +02:00
fe18397acc
wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)
2013-07-22 10:30:44 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
280a87ea69
elsewhere: do not create interface in default param
2012-12-06 17:34:48 +01:00
4bcb39699b
bus/wishbone/sram: accept memories < 32 bits
2012-12-01 13:04:22 +01:00
523816982a
bus/wishbone: add SRAM
2012-12-01 12:59:09 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
ece786d6aa
bus/wishbone: allow specifying existing interface
2012-11-17 19:42:06 +01:00
8de192dfbd
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
b4613d913f
bus/wishbone: remove use of deprecated multimux
2012-07-13 17:17:20 +02:00
8a23451237
PureSimulable
2012-06-12 17:08:56 +02:00
b7a84b3750
wishbone: base TargetModel class
2012-06-10 17:05:10 +02:00
ec501e7797
bus/wishbone: target model
2012-06-10 16:40:33 +02:00
f061b25a24
bus/wishbone/Tap: remove ack feature
2012-06-10 12:46:24 +02:00
11674242c4
Use super() instead of calling parent constructors directly
2012-06-08 18:06:12 +02:00
ab800fa2ed
bus: generic transaction model
2012-03-08 18:14:06 +01:00
0493212124
bus: simplify and cleanup
...
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
2012-02-15 16:30:16 +01:00
0c214b484e
Use double quotes for all strings
2012-02-14 13:12:43 +01:00
a99c2acfa8
Remove explicit bus names and rely on the new automatic namer
2012-01-27 22:20:57 +01:00
076c171c7b
Use meaningful class names
2012-01-20 23:07:32 +01:00
20425703fa
Wishbone: omit fixed LSBs
2012-01-13 17:29:05 +01:00
ba40f58491
corelogic: operator tree
2011-12-22 15:46:19 +01:00
107f03fd4b
Remove uses of declare_signal
2011-12-18 21:47:48 +01:00
c7b9dfc203
fhdl: simpler syntax
2011-12-16 21:30:14 +01:00
39b7190334
Pay a bit more attention to PEP8
2011-12-16 16:02:55 +01:00
92f24b784d
wishbone: decoder: fix slave cyc generation in registered mode
2011-12-13 14:08:39 +01:00
923fc52e68
wishbone: only send ack to the active master in arbiter
2011-12-13 00:25:25 +01:00
4d1a960308
wishbone: decoder + shared bus interconnect
2011-12-09 13:11:52 +01:00
5c7131dc86
wishbone: arbiter
2011-12-08 23:21:25 +01:00
7c99e51b90
Named buses
2011-12-08 19:16:08 +01:00
5720a51dad
wishbone: add missing SEL
2011-12-08 19:09:32 +01:00
c43f3da534
Wishbone declarations
2011-12-08 18:47:41 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jördens