Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
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92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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Sebastien Bourdeauducq
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c08687b9c6
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bus/dfi: filter signals by direction
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2012-02-15 21:48:05 +01:00 |
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Sebastien Bourdeauducq
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fa9cf3e466
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bus: add DFI
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2012-02-15 18:09:14 +01:00 |
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Sebastien Bourdeauducq
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af5230c8ee
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bus: fix simple interconnect
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2012-02-15 16:42:05 +01:00 |
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Sebastien Bourdeauducq
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0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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46b1f74e98
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bus/asmibus/hub: forward data and tag_call
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2012-02-14 14:00:17 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
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Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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e11d9b9322
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bus/wishbone2asmi: cache hits working
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2012-02-13 23:11:16 +01:00 |
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Sebastien Bourdeauducq
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264be80f2d
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Fix syntax errors and other stupid problems
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2012-02-13 22:28:02 +01:00 |
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Sebastien Bourdeauducq
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8a61d9d121
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
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Sebastien Bourdeauducq
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060426cb59
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bus/wishbone2asmi: set WM, and send 0 when inactive
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2012-02-13 16:49:43 +01:00 |
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Sebastien Bourdeauducq
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cad9d3b960
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bus: Wishbone to ASMI caching bridge (untested)
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2012-02-13 16:29:38 +01:00 |
|
Sebastien Bourdeauducq
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7894411418
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bus/asmibus: fix typo
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2012-02-11 20:56:01 +01:00 |
|
Sebastien Bourdeauducq
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ef436a1ec9
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bus/asmibus: add get_slots, fix get_fragment
|
2012-02-10 17:49:06 +01:00 |
|
Sebastien Bourdeauducq
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945d655d45
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bus: ASMI hub (untested)
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2012-02-10 15:21:04 +01:00 |
|
Sebastien Bourdeauducq
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47883675db
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bus/wishbone2csr: truncate WB data
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2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
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a99c2acfa8
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Remove explicit bus names and rely on the new automatic namer
|
2012-01-27 22:20:57 +01:00 |
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Sebastien Bourdeauducq
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076c171c7b
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Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
|
Sebastien Bourdeauducq
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77b3c8e3bb
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bus: list signals
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2012-01-15 15:48:51 +01:00 |
|
Sebastien Bourdeauducq
|
20425703fa
|
Wishbone: omit fixed LSBs
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2012-01-13 17:29:05 +01:00 |
|
Sebastien Bourdeauducq
|
566295dea3
|
csr: use optree
|
2011-12-22 19:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
ba40f58491
|
corelogic: operator tree
|
2011-12-22 15:46:19 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
|
2011-12-18 21:47:48 +01:00 |
|
Sebastien Bourdeauducq
|
1a845d4553
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:49 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
929cc98070
|
wishbone2csr: wait for WB deack
|
2011-12-13 17:38:59 +01:00 |
|
Sebastien Bourdeauducq
|
92f24b784d
|
wishbone: decoder: fix slave cyc generation in registered mode
|
2011-12-13 14:08:39 +01:00 |
|
Sebastien Bourdeauducq
|
0ea7a9b2e6
|
wishbone2csr: fix double-write bug
|
2011-12-13 00:25:46 +01:00 |
|
Sebastien Bourdeauducq
|
923fc52e68
|
wishbone: only send ack to the active master in arbiter
|
2011-12-13 00:25:25 +01:00 |
|
Sebastien Bourdeauducq
|
16a6029a1b
|
bus: fix CSR interconnect data readback
|
2011-12-11 20:17:12 +01:00 |
|
Sebastien Bourdeauducq
|
dad9120653
|
bus: 14-bit CSR addresses
|
2011-12-11 20:16:50 +01:00 |
|
Sebastien Bourdeauducq
|
05d91c7104
|
bus: Wishbone to CSR bridge
|
2011-12-11 15:04:34 +01:00 |
|
Sebastien Bourdeauducq
|
4d1a960308
|
wishbone: decoder + shared bus interconnect
|
2011-12-09 13:11:52 +01:00 |
|
Sebastien Bourdeauducq
|
5c7131dc86
|
wishbone: arbiter
|
2011-12-08 23:21:25 +01:00 |
|
Sebastien Bourdeauducq
|
c1041b9a5f
|
simplebus: export GetSigName function
|
2011-12-08 23:06:04 +01:00 |
|
Sebastien Bourdeauducq
|
7c99e51b90
|
Named buses
|
2011-12-08 19:16:08 +01:00 |
|
Sebastien Bourdeauducq
|
5720a51dad
|
wishbone: add missing SEL
|
2011-12-08 19:09:32 +01:00 |
|
Sebastien Bourdeauducq
|
c43f3da534
|
Wishbone declarations
|
2011-12-08 18:47:41 +01:00 |
|
Sebastien Bourdeauducq
|
a6b86168ce
|
Simple bus base class
|
2011-12-08 18:47:32 +01:00 |
|
Sebastien Bourdeauducq
|
458cfc8623
|
CSR bus definitions
|
2011-12-05 00:16:44 +01:00 |