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Author SHA1 Message Date
enjoy-digital
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn 
build/platforms: Add ice40_hx8k_b_evn from Migen.
 2018-10-04 21:12:33 +02:00
Stafford Horne
ff6de429f0 Fix help for or1k builds 
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
 2018-10-04 23:09:49 +09:00
Stafford Horne
dafdb8df72 Fix compiler warnings from GCC 8.1 
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
 2018-10-04 23:07:48 +09:00
Florent Kermarrec
2be5205463 build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) 2018-10-04 08:17:44 +02:00
Tim 'mithro' Ansell
78414c0588 xilinx/viviado: Allow yosys for synthesis. 2018-10-03 21:58:03 -07:00
Tim 'mithro' Ansell
d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
William D. Jones
9a44f08a3e build/platforms: Add ice40_hx8k_b_evn from Migen. 2018-10-03 20:53:33 -04:00
Tim 'mithro' Ansell
dc7cd75757 build.xilinx: Run phys_opt_design and generate timing report. 
Makes the flow more similar to migen.
 2018-10-03 16:02:43 -07:00
Florent Kermarrec
948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec
15bca4535f targets/sim: fix integrated_main_ram_size when with_sdram 2018-10-02 11:31:08 +02:00
Florent Kermarrec
6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec
975be6686f platforms/genesys2: add eth clock timing constraint 2018-10-01 15:37:34 +02:00
Florent Kermarrec
934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital
9097573e71
Merge pull request #109 from cr1901/xip-improve 
Improve XIP Support
 2018-09-25 15:32:04 +02:00
Florent Kermarrec
082b03016c targets: use new clock abstraction on all 7-series targets 2018-09-25 09:31:30 +02:00
Florent Kermarrec
74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec
91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec
6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec
912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec
baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec
ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec
5415b521be targets/arty: use new clock abstraction module (compile, untested on board) 2018-09-24 22:49:30 +02:00
Florent Kermarrec
63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
William D. Jones
0ff6d58605 Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). 2018-09-24 14:48:54 -04:00
William D. Jones
8106008184 integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. 2018-09-24 12:28:45 -04:00
William D. Jones
db90619067 integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). 2018-09-24 11:04:57 -04:00
Florent Kermarrec
70a32ed86f sim/verilator: add multithread support (default=1) 2018-09-24 12:43:29 +02:00
Florent Kermarrec
7f0d116d88 soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) 2018-09-24 10:59:32 +02:00
Florent Kermarrec
22febe9582 boards/targets: uniformize things between targets 2018-09-24 10:58:10 +02:00
Florent Kermarrec
01b025aafd soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication 2018-09-24 08:01:32 +02:00
Florent Kermarrec
b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec
2d785cb0ac boards/plarforms: fix issues found while testing simple design on all platforms 2018-09-24 02:03:30 +02:00
Florent Kermarrec
c88029d330 soc_core: add uart-stub argument 2018-09-24 02:01:15 +02:00
Florent Kermarrec
e9ed737037 ease RemoteClient import 2018-09-23 10:23:00 +02:00
Sean Cross
6f25a0d8a1 csr: use external csr_readl()/csr_writel() if present 
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.

With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:55:09 +02:00
Sean Cross
9a252e367c csr: use readl()/writel() accessors for accessing mmio 
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:54:46 +02:00
William D. Jones
9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash. 
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
 2018-09-21 10:23:14 -04:00
Florent Kermarrec
15e584d880 targets/sim: generate analyzer.csv 2018-09-20 12:20:48 +02:00
Florent Kermarrec
cde72603a1 targets/sim: generate csr.csv 2018-09-20 11:17:18 +02:00
Florent Kermarrec
f62df5023f targets/sim: add rom-init 2018-09-20 01:14:00 +02:00
Florent Kermarrec
1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec
9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec
a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec
934b08ede8 targets/sim: merge in a single class and ease configuration 2018-09-19 23:59:15 +02:00
Florent Kermarrec
bd42b18856 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-09-19 19:21:14 +02:00
Florent Kermarrec
3e77ae788f targets: replace MiniSoC with EthernetSoC 2018-09-19 19:19:50 +02:00
Florent Kermarrec
badd992469 targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) 2018-09-19 19:17:32 +02:00
enjoy-digital
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull 
Icestorm Improvements
 2018-09-18 08:19:09 +02:00
William D. Jones
5c83c88128 Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. 2018-09-17 21:17:24 -04:00
Florent Kermarrec
9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
Florent Kermarrec
a44bedd557 bios/sdram: add missing #ifdef 2018-09-13 06:30:37 +02:00
Florent Kermarrec
0e68daebf3 targets: self.pll_sys --> pll_sys 2018-09-13 05:31:35 +02:00
Florent Kermarrec
1468b9f3ba bios/sdram: show all read scans when failing. 2018-09-13 05:26:51 +02:00
Florent Kermarrec
07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec
df3f003ecd soc_sdram: update with litedram 2018-09-09 02:13:00 +02:00
enjoy-digital
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram 
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
 2018-09-08 03:55:23 +02:00
William D. Jones
bd70ba278b Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. 2018-09-07 21:49:24 -04:00
enjoy-digital
69716852f1
Merge pull request #100 from cr1901/tinyprog-fix 
lattice/programmer: Use --program-image option with tinyprog if addre…
 2018-09-08 03:48:04 +02:00
Florent Kermarrec
12a8944711 soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) 2018-09-07 11:51:17 +02:00
Florent Kermarrec
2b786065b1 targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen 2018-09-07 10:37:15 +02:00
William D. Jones
c812321a93 lattice/programmer: Use --program-image option with tinyprog if address is given. 2018-09-07 04:05:49 -04:00
Jean-François Nguyen
26963d62fa libnet/microudp: (WIP) fix endianness issues 2018-09-06 18:43:55 +02:00
Jean-François Nguyen
22c0131324 fix typo and unused include 2018-09-06 17:07:14 +02:00
Florent Kermarrec
fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Jean-François Nguyen
8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec
1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
Tim Ansell
c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx 
build/platforms: Add TinyFPGA BX board and programmer.
 2018-09-03 20:49:33 -07:00
William D. Jones
2949262449 build/platforms: Add TinyFPGA BX board and programmer. 2018-09-03 23:39:40 -04:00
William D. Jones
ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
William D. Jones
7af89efc70 lattice/icestorm: Add nextpnr pnr as alternate pnr tool. 2018-08-28 05:17:32 -04:00
Tim Ansell
ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones
3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec
759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec
09776b77e6 sim: run as root only when needed (ethernet module present) 2018-08-22 15:20:28 +02:00
Florent Kermarrec
06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00
Florent Kermarrec
ee26f8c5ae soc_sdram: cosmetic 2018-08-22 13:40:22 +02:00
Florent Kermarrec
2db5424ae6 soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) 2018-08-22 13:28:23 +02:00
Florent Kermarrec
45e9a42c7e soc_core: add cpu_endianness 2018-08-21 19:10:22 +02:00
Florent Kermarrec
3877d0f111 builder: get_sdram_phy_header renamed to get_sdram_phy_c_header 2018-08-21 18:15:57 +02:00
Florent Kermarrec
c64e44ef3f soc_sdram: use new LiteDRAMWishbone2Native and port.data_width 2018-08-21 14:52:28 +02:00
Florent Kermarrec
2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec
eecc6f68ed soc/integration: move sdram_init to litedram 2018-08-20 15:36:51 +02:00
Florent Kermarrec
077f939169 Vexriscv: update csr-defs.h 2018-08-18 14:15:43 +02:00
Florent Kermarrec
4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec
9547938527 bios/sdram: changes to ease manual read window selection 2018-08-18 13:45:22 +02:00
Florent Kermarrec
a760322fbd litex_server: allow multiple clients to connect to the same server 2018-08-17 16:09:08 +02:00
Florent Kermarrec
8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec
cb5b4ac468 bios/boot: flush all caches before running from ram 2018-08-16 19:47:43 +02:00
Florent Kermarrec
650ac18685 sim/verilator: catch ctrl-c on exit and revert default termios settings 2018-08-16 15:13:27 +02:00
Florent Kermarrec
0831ad5492 cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf 2018-08-16 10:04:09 +02:00
Florent Kermarrec
1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
Peter Gielda
3c7890cdd4
Fix generating csr.csv file 
Fix generating csr.csv file when no absolute path is given.
 2018-08-12 13:37:39 +02:00
Florent Kermarrec
9fa234da50 soc/intergration/cpu_interface: typo 2018-08-08 08:53:54 +02:00
Florent Kermarrec
22f645adc1 bios/main: use edata instead of erodata 2018-08-07 09:02:09 +02:00
Florent Kermarrec
580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec
0429ee9f8f soc/software/bios: add reboot command 2018-08-06 12:23:50 +02:00
Florent Kermarrec
da75159814 soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers 2018-08-06 12:23:16 +02:00
Florent Kermarrec
8ba5625227 soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. 2018-08-06 12:21:18 +02:00
Florent Kermarrec
c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
Sean Cross
fb145daced tools: remove vexriscv_debug 
This program is no longer needed.

The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.

This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:25:33 +08:00