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622 commits

Author SHA1 Message Date
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec
c3652935d9 build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
Florent Kermarrec
121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec
39ffa532b0 xilinx/programmer: fix programmer 2018-05-01 00:44:13 +02:00
Florent Kermarrec
c001b8eaf6 build/xilinx/vivado: add vivado ip support 2018-04-12 17:55:46 +02:00
Florent Kermarrec
43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec
d7c7474670 gen/sim: fix import to use litex simulator instead of migen simulator 2018-04-04 15:40:53 +02:00
Florent Kermarrec
b7f7c8d159 build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC" 2018-03-12 09:33:05 +01:00
Florent Kermarrec
4324c6f666 bios/sdram: update kuddrphy initialization procedure 2018-03-08 13:54:30 +01:00
Florent Kermarrec
90dcd45f0b soc/software/main: go to new line at startup 2018-03-07 21:39:10 +01:00
Florent Kermarrec
6706b24167 software/bios/main: add missing space 2018-03-07 15:24:39 +01:00
Florent Kermarrec
2a50a8021a soc/integration/soc_core: improve error message for missing csrs 2018-03-05 09:59:06 +01:00
Tim 'mithro' Ansell
5ef34500f7 Improving error message when csr name is not found. 
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```

Now;
```
Traceback (most recent call last):
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
    return self.csr_map[name]
KeyError: 'ddrphy'

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  ...
  File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
    mapaddr = self.address_map(name, None)
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
    ) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.

Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py

Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
 2018-03-03 16:02:44 -08:00
enjoy-digital
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths 
xilinx/vivado: Provide a fallback mechanism for using the same root f…
 2018-03-03 08:29:18 +01:00
enjoy-digital
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial 
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
 2018-03-03 08:28:57 +01:00
William D. Jones
2b00b7eba4 xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. 2018-03-02 21:48:49 -05:00
Florent Kermarrec
fa6b256198 build/xilinx/platform: fix merge 2018-03-03 00:07:50 +01:00
William D. Jones
d40c57739c boards/arty_s7: Fix IOStandard on System Clock. 2018-03-02 13:35:43 -05:00
Florent Kermarrec
0332f73a7b build/xilinx/vivado: revert toolchain_path 2018-02-28 23:45:26 +01:00
Florent Kermarrec
2ff50a8882 build: fix merge 2018-02-28 23:10:24 +01:00
Florent Kermarrec
64e4e1ce84 build: merge with migen.build 27beffe7 2018-02-28 16:49:12 +01:00
Florent Kermarrec
0edfd9b901 boards/kcu105: regroup sfp tx and rx 2018-02-28 14:11:58 +01:00
William D. Jones
e71593d67e platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it 
optional via `add_extension`.
 2018-02-27 18:41:35 -05:00
Florent Kermarrec
1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec
43164b9a2c remove migen fork from litex 2018-02-23 13:37:26 +01:00
Sergiusz Bazanski
688f26cc32 Change AXI interface and tidy code 
Inspired by parts of https://github.com/peteut/migen-misc/
 2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6 Preliminary AXI4Lite CSR bridge support 
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
 2018-02-20 21:27:51 +00:00
enjoy-digital
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection 
Top module selection (for Verilator and Diamond)
 2018-02-19 12:27:25 +01:00
enjoy-digital
7b5bd4041a
Merge pull request #57 from rohitk-singh/master 
WIP - BIOS: Flashboot without main ram
 2018-02-10 21:37:38 +01:00
Florent Kermarrec
c14502807e board/targets/nexys4ddr: use MT47H64M16 2018-02-06 19:17:54 +01:00
Florent Kermarrec
95ebba428c boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 2018-02-06 19:08:46 +01:00
Florent Kermarrec
ee4fa597b4 boards: add nexys4ddr 2018-02-06 14:43:20 +01:00
enjoy-digital
2ecd1b0666
Merge pull request #61 from PaulSchulz/master 
platform/arty.py: Move Pmod definitions to 'connectors' section.
 2018-01-26 01:58:37 +01:00
William D. Jones
4607e5323f boards/platforms: Add Arty S7 Board. 2018-01-25 18:36:32 -05:00
Paul Schulz
0ac35300c4 Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream 2018-01-24 13:32:42 +10:30
Florent Kermarrec
4f2725809e software/common: revert PYTHON to python3 (since breaking things) 2018-01-23 10:39:13 +01:00
Florent Kermarrec
4e168221d8 bios: fix riscv processor print 2018-01-23 10:33:05 +01:00
Florent Kermarrec
d448874879 sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) 2018-01-23 10:28:16 +01:00
Paul Schulz
3ac28ed6f7 platform/arty.py: Move Pmod definitions to 'connectors' section. 2018-01-23 16:11:25 +10:30
Sergiusz Bazanski
ef511e7edc Specify top-level module in Lattice Diemond build script. 
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
 2018-01-23 01:17:04 +00:00
Sergiusz Bazanski
ef6c517dad Build top module as 'dut' in Verilator and set it as top-level. 
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
 2018-01-23 01:15:28 +00:00
Sergiusz Bazanski
21bd26dcdd Allow for multiple synthesis directives in specials. 
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.

To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
 2018-01-23 00:27:49 +00:00
Florent Kermarrec
67f8718b26 minor cleanup 2018-01-23 00:35:20 +01:00
Sergiusz Bazanski
6daf3eabc5 Implement IRQ software support for RISC-V. 
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.

It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
2108c97b9b Import PicoRV32-specific instruction macros. 
These come from the PicoRV32 repo and are released under the public
domain [1].

[1] - 70f3c33ac8/firmware/custom_ops.S
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
cf74c781f4 Write init files that respect CPU's endianness. 
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7176492231 Set the MABI and MArch of the riscv target. 
Again, this should be tunable, and synchronized with the core settings.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
75e230aae7 Replace __riscv__ macros with __riscv. 
The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Ewen McNeill
75e7f9505a BIOS: Flashboot without main ram 
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
 2018-01-20 15:05:47 +11:00
Florent Kermarrec
3a5f93db5d software/bios: add litex logo 2018-01-19 18:41:13 +01:00
William D. Jones
c553fe2bf3 Add mimasv2 platform (pulled from litex-buildenv). 2018-01-19 06:16:04 -05:00
Tim 'mithro' Ansell
ead88ed66d Support forcing colorama colors on. 
This is needed if you want colors but are using pipes and similar.
 2018-01-18 14:41:45 +11:00
Tim Ansell
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port 
BIOS: Support alternate TFTP server port
 2018-01-18 13:40:28 +11:00
Ewen McNeill
5ce8ca8e9b BIOS: TFTP: try UDP/69 if specified port fails 2018-01-18 13:10:28 +11:00
Ewen McNeill
cb31266500 BIOS: set TFTP_SERVER_PORT from enviroment 2018-01-18 13:09:34 +11:00
Ewen McNeill
97f381baa6 BIOS: allow BIOS to specify TFTP server port 
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions.  Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
 2018-01-18 12:03:35 +11:00
enjoy-digital
e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling 
Include the ethernet related header files conditionally
 2018-01-16 21:37:24 +01:00
Felix Held
21ad435def Include the ethernet related header files conditionally 
Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
 2018-01-16 14:33:49 +11:00
Tim 'mithro' Ansell
3d40ad0a82 soc_core: Don't fail if name is the same. 
Otherwise you can't override the UART with another UART, you get an
error like;

```
  File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
    interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
 2018-01-13 19:10:57 +11:00
Tim Ansell
bebaef1e25
Merge pull request #48 from mithro/fix-constants 
cpu_interface: Fix indenting on constant generation.
 2018-01-13 19:07:04 +11:00
Tim 'mithro' Ansell
f6f73cf13c cpu_interface: Fix indenting on constant generation. 
This was preventing constants from getting added to the csr.h header
file.
 2018-01-13 19:05:26 +11:00
Felix Held
6318a2b29a Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:19:36 +11:00
Chris Ballance
782711e5a9 bios/sdram: make read leveling robust for KUS SDRAM 
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
 2018-01-12 19:23:08 +01:00
Tim Ansell
5c95c8ead0
Merge pull request #44 from felixheld/nexys_video-dram-fix 
Fix DDR3 on nexys_video
 2018-01-12 14:08:03 +11:00
Felix Held
9eb1beea04 fix DDR3 on arty 2018-01-12 13:54:10 +11:00
Felix Held
4a3454107a fix DDR3 on nexys_video 2018-01-12 13:33:13 +11:00
Felix Held
23585385c0 fix the unsupported programmer case for kc705 and minispartan6 2018-01-11 18:15:11 +11:00
Florent Kermarrec
10000eb607 build/xilinx/vivado: only generate constraints that are not empty 2018-01-08 17:03:19 +01:00
Florent Kermarrec
5681a3c1a9 bios/sdram: revert capability to do manual read leveling since still needed with some targets 2018-01-08 12:04:33 +01:00
Florent Kermarrec
03eb137449 bios/sdram: fix data error reporting 2018-01-08 11:43:49 +01:00
Florent Kermarrec
22ff745027 bump year 2018-01-08 11:43:13 +01:00
Florent Kermarrec
ee6b33e9d3 build: add Inverted property to IOs to ease inverting signals and propagate property to cores 2018-01-06 01:33:02 +01:00
Florent Kermarrec
621aaf6988 soc/integration/soc_core: avoid removing uart interrupts (break some designs) 2017-12-30 18:41:49 +01:00
enjoy-digital
377af99678
Merge pull request #40 from mithro/or1k-linux 
cpu: Adding "variant" support.
 2017-12-30 11:19:12 +01:00
enjoy-digital
f8a07c5d3c
Merge pull request #41 from cr1901/python-3.6 
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
 2017-12-30 11:17:41 +01:00
William D. Jones
ff0ad9a622 fhdl/tracer: Import Python 3.5/3.6 version guards from Migen. 2017-12-29 19:56:52 -05:00
Tim 'mithro' Ansell
44650dffd8 cpu: Adding "variant" support. 
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.

For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.

Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
 2017-12-30 01:18:51 +01:00
Greg Darke
bbd15ca567 Wait longer before giving up on the 2nd tftp block. 
Previously we would wait the same number of iterations as it took us to
receive the first data block after sending the request. When using the
build in tftp server in qemu, the first wait loop succeeds (and thus
breaks when 'i' is still 0.

Since the counter was never reset between the first and second data
block, under qemu the tftp_get call would fail before ever checking if
we have received the second block of data.

Now that we initialise 'i' to 12M, we ensure that we wait the same
amount of time for the second data block as it previously did for the
third (and subsequent) blocks.
 2017-12-29 23:56:32 +01:00
Florent Kermarrec
0a2d38ecd2 bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done 2017-12-29 17:13:58 +01:00
Florent Kermarrec
b78a4760bb soc/integration/builder: don't build bios is user is providing rom data 2017-12-28 22:42:58 +01:00
enjoy-digital
5d98a60e6e
Merge pull request #38 from cr1901/mercury 
Add Mercury baseboard support from Migen, import fixes.
 2017-12-27 17:52:37 +01:00
bunnie
282f22f09e Add tracelength report generation by default to help with board layout 2017-12-27 22:40:39 +08:00
Florent Kermarrec
b463b2169b boards/platforms/tinyfpga_b: add defaut serial pins 2017-12-27 00:26:30 +01:00
Florent Kermarrec
fe2564e921 build/lattice/icestorm: fix missing toolchain_path 2017-12-27 00:26:07 +01:00
William D. Jones
5a2c92ba80 Add TinyFPGA platform based on Migen. 2017-12-27 00:00:05 +01:00
William D. Jones
f096030fc8 Import Icestorm backend improvements from Migen. 2017-12-26 23:57:13 +01:00
Florent Kermarrec
e7015e4191 soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file) 2017-12-26 18:11:47 +01:00
Florent Kermarrec
a3390bb403 build/xilinx/programmer: fix settings in run_vivado (update) 2017-12-19 10:29:29 +01:00
William D. Jones
dd6ca87561 Add Mercury baseboard support from Migen, import fixes. 2017-12-18 19:30:25 -05:00
Florent Kermarrec
4c82eb549f build/xilinx: add support for edif/ngc files 2017-12-16 13:20:45 +01:00
Florent Kermarrec
b31d0f37db cpu/picorv32: adapt to current version, some cleanup 2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a cpu: cleanup wrappers 2017-12-10 02:52:01 +01:00
Florent Kermarrec
43429560d4 soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code 2017-12-08 10:18:01 +01:00
Florent Kermarrec
27d37fa95d targets/sim: fix 2017-12-06 22:22:05 +01:00
Florent Kermarrec
284b16e2c1 soc/integration/soc_core: make nmi interrupt optional 2017-12-03 23:07:41 +01:00
Florent Kermarrec
c1eba9a6cc soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware 2017-11-24 13:16:58 +01:00
Florent Kermarrec
831b489fd3 soc/interconnect/stream: fix specific cases for last/first signal in UpConverter 2017-11-23 17:58:02 +01:00
Florent Kermarrec
c3d902ef42 soc/software/bios/sdram: add Kintex Ultrascale support 2017-11-08 12:59:38 +01:00
Florent Kermarrec
2665a83288 soc/interconnect/stream: expose depth on SyncFIFO 2017-10-30 22:56:09 +01:00
Tim 'mithro' Ansell
56ef229029 Make the interrupt dicts read only. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
295e78ee9e Make it harder to have conflicting interrupts. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
ff72757b87 Bump the IRQ for liteeth based targets. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
73e0036b99 Change the default IRQs. 
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
   future.

 * Use IRQ 2 for the LiteX. This matches the standard mor1k config which
   connects the UART to IRQ 2.

This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
e07bd71b16 build/xilinx: Fixing settings finding. 
* Better error messages.
 * Search correct directories;
   - XXX/Vivado/<version>
   - XXX/<version>/ISE_DS/
 2017-10-16 18:25:51 +11:00
Florent Kermarrec
db6c88bbef soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases) 2017-10-12 11:30:56 +02:00
Tim 'mithro' Ansell
2c013948b1 Output better error message for flash_proxy. 2017-10-07 12:14:00 +11:00
Tim 'mithro' Ansell
279ec488e3 bios: Print location jumping too. 
Makes it easier to  understand what is happening (and that the BIOS is
jumping to the right place).
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
8152673d18 common: Compile with debugging symbols on. 
Debugging symbols are useful when using GDB :-)
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
b1b6a74170 or1k: Use EXCEPTION_STACK_SIZE of 256bytes. 
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.

We also need 128 bytes to store the 32 registers.
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
07a9df3586 bios: Declare dependency on linked in .a files. 2017-10-06 20:38:44 +11:00
William D. Jones
e558473119 Add iCEStick board. Tested with litescope. 2017-10-04 01:59:53 -04:00
William D. Jones
c3383f47ba Port IceStorm backend from Migen. 2017-10-03 22:48:44 -04:00
Florent Kermarrec
ba1bf20f37 soc/cores: add cordic 2017-09-29 12:07:43 +02:00
enjoy-digital
878380abba Merge pull request #28 from enjoy-digital/eb-docs-2 
More docs for etherbone packet fields.
 2017-09-26 12:33:57 +02:00
Florent Kermarrec
e42ab27f30 gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command 2017-09-13 13:47:25 +02:00
Florent Kermarrec
2a8f6edded soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier 2017-09-06 15:39:54 +02:00
Tim Ansell
3a656c61d9 More docs for etherbone packet fields. 
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
 2017-09-01 23:57:34 +10:00
Tim Ansell
c125ea6440 Adding a little docs to field descriptions. 2017-09-01 23:27:58 +10:00
Florent Kermarrec
8f3dcf90ab soc/software/bios/sdram: add optional memtest debug traces 2017-08-18 09:42:27 +02:00
Florent Kermarrec
c02de1632b soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists 2017-07-27 18:22:01 +02:00
Florent Kermarrec
04646b24ed soc/interconnect/stream: fix make_m2s for reset_less 2017-07-24 18:18:35 +02:00
Florent Kermarrec
9509d9e361 gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers. 
read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
 2017-07-24 13:39:08 +02:00
enjoy-digital
f25e46c428 Merge pull request #26 from q3k/diamond-linux-support 
Add Diamond toolchain support for Linux.
 2017-07-20 14:41:05 +02:00
Sergiusz Bazanski
503df5e93e Add Diamond toolchain support for Linux. 
This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
 2017-07-20 13:21:10 +01:00
Florent Kermarrec
756554371a soc/tools/remote/litex_server: allow multiple instance of server 2017-07-19 21:18:12 +02:00
Florent Kermarrec
0b6d38abe9 build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer 2017-07-19 14:54:19 +02:00
Florent Kermarrec
d05d170b75 soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False 2017-07-19 12:18:35 +02:00
Florent Kermarrec
20c859d45c soc/tools/remote/etherbone: speed optimization (~20/30%) 2017-07-17 00:25:58 +02:00
Florent Kermarrec
bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
Sergiusz Bazanski
1885e50d54 Add Versa ECP5-5G Platform. 2017-07-05 15:01:07 +01:00
Florent Kermarrec
0894f9e6f7 targets: cleanup arty/nexys_video/kc705 and use better ddr3 timings on arty/nexys_video (found using the new bitslip/delay finder tool) 2017-07-04 09:01:29 +02:00
Florent Kermarrec
fe535db5ab merge migen ee0e709 changes 2017-07-04 08:15:40 +02:00
Florent Kermarrec
c6f6d7b491 soc/interconnect/wishbonebridge: reset_less optimizations 2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4 soc/interconnect/stream_packet: reset_less optimizations 2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3 soc/interconnect/stream: improve reset_less support for streams 2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8 soc/interconnect/stream: use reset_less attr of signal for payload and param 2017-06-28 23:10:45 +02:00
Florent Kermarrec
bd876d4cd6 merge migen 9a6fdea3 changes 2017-06-28 22:47:13 +02:00
Florent Kermarrec
4d664730fe soc/software/libbase: fix get_ident 2017-06-28 18:10:56 +02:00
Florent Kermarrec
e61d9eabc6 board/targets/sim: add identifier 2017-06-28 18:08:37 +02:00
Florent Kermarrec
4433e2449a litex/build/sim: cleanup modules 2017-06-28 18:01:04 +02:00
Florent Kermarrec
c3710ec139 build/sim: cleanup serial2console and fix terminal mode 2017-06-28 17:38:09 +02:00
Florent Kermarrec
5ece895fd3 litex/build/sim: add README 2017-06-28 16:55:32 +02:00
Florent Kermarrec
4a0a431119 litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex) 2017-06-28 16:28:45 +02:00
Florent Kermarrec
ab6f4de521 litex/build/sim: small cleanup 2017-06-28 16:25:56 +02:00
Florent Kermarrec
1d8298af94 litex/build/sim: add tapcfg submodule for ethernet 2017-06-28 16:18:15 +02:00
Pierre-Olivier Vauboin
8510b12e93 litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept) 2017-06-28 16:14:13 +02:00
Florent Kermarrec
6631aa5385 boards/platforms/arty: add pmods 2017-06-23 10:50:37 +02:00
Florent Kermarrec
1364ac3657 soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
Florent Kermarrec
f720ef5631 soc/tools: simplify litex_server usage and integrage udp, pcie 2017-06-22 11:30:33 +02:00
Florent Kermarrec
41a91829eb soc/tools: syntax fix on comm_pcie, import in __init__.py 2017-06-22 11:29:57 +02:00
Florent Kermarrec
c82c1d103f soc/tools: fix debug prints of comm_pcie 2017-06-22 10:33:08 +02:00
Florent Kermarrec
684ae45dbe soc/tools: remove csr builder from comm_udp (we should use litex_server) 2017-06-22 10:32:39 +02:00
Florent Kermarrec
4ea7026747 gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie 2017-06-10 21:53:53 +02:00
Florent Kermarrec
c44a4b051f soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases) 2017-06-09 19:35:48 +02:00
Florent Kermarrec
c19c4b711b soc/cores/identifier: remove additionnal first character 2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95 soc/cores/uart: add uart multiplexer 2017-06-05 19:36:30 +02:00
Florent Kermarrec
157c2b17bc boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port 2017-06-05 15:13:21 +02:00
Florent Kermarrec
a36986a501 gen/fhdl/verilog: list available clock domains on keyerror 2017-06-05 14:33:46 +02:00
Florent Kermarrec
931ea5ac75 gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise 
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
 2017-06-01 19:00:22 +02:00
Florent Kermarrec
85aea62d74 soc/core: add frequency meter 2017-06-01 00:39:19 +02:00
Florent Kermarrec
ff2a9c2176 gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned) 2017-05-31 13:23:31 +02:00
Florent Kermarrec
4bc6cf6165 soc/cores: dna/xadc: add missing copyright 2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6 soc/cores: add dna and xadc (for 7-series, add support for others fpgas?) 2017-05-16 21:02:33 +02:00
Tim 'mithro' Ansell
5f9ff09c08 vivado: Fix segfault with or1k. 
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
  File "./make.py", line 82, in <module>
```
 2017-04-29 16:44:18 +10:00
Florent Kermarrec
bedd428d9d soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing. 2017-04-26 13:49:16 +02:00
Florent Kermarrec
bb582619eb gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer 2017-04-25 15:13:47 +02:00
Florent Kermarrec
0daeff8689 gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal) 2017-04-25 10:56:19 +02:00
Florent Kermarrec
456cce3ec6 gen/genlib/cdc: import gcd from math and not fractions (deprecated) 2017-04-25 10:55:13 +02:00
Florent Kermarrec
4c7d460475 litex/gen/util/misc: import gcd from math and not fractions (deprecated) 2017-04-24 19:25:24 +02:00
Florent Kermarrec
c0800d25a6 soc/integration/builder.py: don't take care of ROM when compile_software is forced to False 2017-04-24 19:12:30 +02:00
Florent Kermarrec
b34f74397a soc/cores: add code_8b10b from misoc 2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280 soc/cores: move flash cores to cores directory 2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa soc: move uart to a single file 2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397 soc/cores: add new spi master, remove obsolete one 2017-04-19 10:22:35 +02:00
Florent Kermarrec
f73eb5fe71 gen/genlib/misc: add BitSlip 2017-04-19 09:55:19 +02:00
Florent Kermarrec
b708b9cfba gen/genlib/cdc: add gearbox 2017-04-19 09:54:51 +02:00
Florent Kermarrec
e27bc936ef boards/platforms: add vadj, change user_sw, user_btn IOStandard to LVCMOS25 2017-04-03 17:36:45 +02:00
Florent Kermarrec
5efd6a8412 soc/interconnect/stream_packet.py: make error payload optional on Packetizer 2017-03-28 12:21:54 +02:00
Florent Kermarrec
d173d946b7 boards/platforms/papilio_pro: fix imports 2017-03-27 10:40:29 +02:00
Florent Kermarrec
b6bc040142 boards/platforms/arty: add spi pins 2017-03-20 16:11:00 +01:00
Tim 'mithro' Ansell
4ee7019852 soc_core: Add CPU_RESET_ADDR as a constant. 
So we can do a "soft reset" by jumping to this address.
 2017-03-12 22:49:36 +11:00
Florent Kermarrec
c69012d713 boards/platforms/kcu105: add user_sma_gpio 2017-03-08 16:52:31 +01:00
Tim 'mithro' Ansell
36bb0f4f3a Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2017-03-05 19:01:03 +11:00
William D. Jones
4dea714ec7 Add Mercury development board (port from MiSoC) 2017-02-21 05:06:51 -05:00
Florent Kermarrec
187d9577ab boards/platforms: fix IOStandard on sfp_tx_disable_n pins 2017-02-20 18:34:49 +01:00
Florent Kermarrec
1cda83f11b build/xilinx/programmer: add target parameter to load_bitstream to select jtag programmer 2017-02-20 17:37:03 +01:00
Florent Kermarrec
d8c7702be8 boards/platforms/kcu105: add sma/sfp ios 2017-02-20 15:55:41 +01:00
Florent Kermarrec
9774cbd20e boards/platforms/kc705: add sma/sfp/xadc ios 2017-02-20 12:22:23 +01:00
Florent Kermarrec
60f7e9c14f build/lattice/diamond: add jedec file generation 2017-02-18 17:33:50 +01:00
Florent Kermarrec
384f4f428e build/xilinx/vivado: set_property library only supported for vhdl 2017-02-17 11:42:55 +01:00
Florent Kermarrec
ac70083453 boards/plaforms: add FMC LPC connector to nexys_video 2017-02-16 19:16:07 +01:00
Florent Kermarrec
afd0a0c7f3 boards/targets: add dram to arty and nexys_video 2017-02-16 18:52:27 +01:00
Florent Kermarrec
5fde6d6d3d build/lattice/diamond: remove use of tools.mkdir_noerror 2017-02-16 11:48:22 +01:00
Florent Kermarrec
3711ae0615 boards/targets: remove build and load parameters on arty and nexys_video (consistency with others targets) 2017-02-10 12:32:33 +01:00
Florent Kermarrec
c98a90520e boards/kc705: store bios in flash as it's done for others litex targets (we could use flash in custom designs) 2017-02-10 09:30:10 +01:00
Florent Kermarrec
a3ef0fd53d boards/platforms/kcu105: add ddr4 dram pinout 2017-02-09 15:26:22 +01:00
Florent Kermarrec
892f019871 boards/platforms/nexys_video: fix IOStandards on hdmi_in 2017-02-06 18:18:36 +01:00
Florent Kermarrec
be4fbdcaeb boards/platforms/kcu105: add DP4 to DP7 to HPC connector 2017-02-02 18:44:12 +01:00
Florent Kermarrec
4177023a20 build/xilinx/programmer: remove open_hw_target parameters on VivadoProgrammer (now works for ultrascale) 2017-02-01 14:33:26 +01:00
Florent Kermarrec
790020de9f soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported) 2017-02-01 12:21:56 +01:00
Florent Kermarrec
7b6f06cc07 boards/platforms/kcu105: fix GBTCLK0_M2C/GBTCLK1_M2C pins 2017-02-01 11:58:41 +01:00
Florent Kermarrec
0b86295c6d boards/platforms/kcu105: add user_sma_clock_p/n 2017-02-01 10:36:57 +01:00
Florent Kermarrec
df464aeaf3 boards/platforms/kcu105: add user_btns, user_dip_btns, clk300, i2c, spi_flash, rotary hdmi, pcie 2017-01-31 09:57:36 +01:00
Florent Kermarrec
194cf6c959 boards/platforms/kcu105: add LPC connector 2017-01-31 09:28:22 +01:00
Florent Kermarrec
c2dd7b1235 boards/platforms/kcu105: add user sma clock and HPC connector 2017-01-30 18:47:22 +01:00
Florent Kermarrec
f0020a6490 boards/platforms: add minimal kcu105 platform 2017-01-30 17:33:19 +01:00
Florent Kermarrec
de336a86e5 soc/integration/soc_core: use cpu_reset_address = self.mem_map["rom"] when using integrated_rom 2017-01-30 14:10:57 +01:00
Florent Kermarrec
67645ce7dd boards/platform/arty: add spiflash_4x/spiflash_1x to test SpiFlashDualQuad and SpiFlashSingle 2017-01-26 13:28:19 +01:00
Florent Kermarrec
4b77b850ce add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad 2017-01-26 13:28:18 +01:00
Tim 'mithro' Ansell
2444c090ab Adding paths for vivado. 2017-01-20 10:30:34 +11:00
enjoy-digital
6d0096a18e Merge pull request #14 from mithro/spiflash2 
spi_flash: fix bitbang with spi_width=1
 2017-01-17 04:41:05 +01:00
Florent Kermarrec
455cb3ebe3 soc/software/main: fix double serialboot (merge issue) 2017-01-17 04:37:18 +01:00
Tim 'mithro' Ansell
bd0eb48357 Fixing missing csr_constant/config support. 
Missed as part of misoc merge at ff31959aea.
 2017-01-14 19:24:04 +11:00
Tim 'mithro' Ansell
9c0e978556 Fixing accidental revert in merge commit. 2017-01-14 00:13:53 +11:00
Florent Kermarrec
ff31959aea merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00
enjoy-digital
2507eff890 Merge pull request #15 from joeladdison/master 
Add strcasecmp function to lib
 2017-01-12 04:24:28 +01:00
Florent Kermarrec
f0202db90f gen/genlib/cdc: add GrayDecoder from misoc 2017-01-12 04:15:33 +01:00
Joel Addison
31dbd35c2e Add strcasecmp function to lib 2017-01-12 14:00:05 +11:00
Florent Kermarrec
ab5b9389b7 soc/tools/litex_term.py: fix reader for c = b"\r" case 2017-01-11 01:56:31 +01:00
Florent Kermarrec
30f7dd69bd soc/interconnect/stream/: add busy signal to PipelinedActor 2017-01-10 02:18:21 +01:00
Sebastien Bourdeauducq
e39c470bbc spi_flash: fix bitbang with spi_width=1 2016-12-26 14:11:49 +01:00
Tim 'mithro' Ansell
b81839bf1a Raise AttributeError. 
Makes hasattr work correctly.
 2016-12-23 11:14:18 +01:00
Tim 'mithro' Ansell
284c94f1d3 Fix Makefile dependency inclusion for other software. 2016-12-19 14:29:33 +01:00
enjoy-digital
ffc342f49c Merge pull request #11 from mithro/file-dont-change 
Only require rebuild on actual changes
 2016-12-17 14:43:34 +01:00
Tim 'mithro' Ansell
1f6dc446d2 Allow CSRElement objects to be autocompleted. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
722edfe9e8 Provide csr_data_width via the constants. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
8bccd2d988 bios: Include dependency rebuild info. 2016-12-17 14:14:14 +01:00
Tim 'mithro' Ansell
46bbec5494 main.o is not a phony target. 2016-12-15 19:56:58 +01:00
Tim 'mithro' Ansell
4522157ddd Use write_to_file helper. 2016-12-15 19:51:36 +01:00
Tim 'mithro' Ansell
8179a9ea2e Don't modify file if contents hasn't changed. 2016-12-15 19:14:12 +01:00
Tim 'mithro' Ansell
9d716def9d Make the csv directory if it doesn't exist. 2016-12-15 17:19:51 +01:00
Florent Kermarrec
8b5166f294 litex/boards: add machxo3 starter kit platform 2016-12-02 17:28:32 +01:00
Florent Kermarrec
873e50430e litex/build: move xcf_template to platform (xcf is specific to platform) 2016-12-02 17:23:40 +01:00
Florent Kermarrec
daa9473809 soc/software/bios/main: revision command becomes ident 2016-11-30 15:45:06 +01:00
Florent Kermarrec
0f57451f30 soc/software/bios: remove dataflow 2016-11-30 15:44:30 +01:00
whitequark
460185fa8e litex_term: nicer progress bar 2016-11-30 15:36:13 +01:00
Florent Kermarrec
4f3ce6db2b build/xilinx/vivado: fix settings source on linux 2016-11-30 15:28:38 +01:00
enjoy-digital
7bb2be41e8 Merge pull request #9 from mithro/vprintf-fix 
libbase: Adding missing vprintf function.
 2016-10-30 09:43:43 +01:00
Tim 'mithro' Ansell
548fd33d20 libbase: Adding missing vprintf function. 
Fixes #8.

```
int vprintf(const char *format, va_list ap);

The functions vprintf(), vfprintf(), vsprintf(), vsnprintf() are equivalent to
the functions printf(), fprintf(), sprintf(), snprintf(), respectively, except
that  they  are  called  with  a  va_list instead of a variable number of
arguments.
```
 2016-10-30 16:25:06 +11:00
Tim 'mithro' Ansell
35ba9cf735 soc/software/Makefile: Fix Makefile depend generation. 
Previously the flags were not actually set and the *.d files were never
actually generated.
 2016-10-28 01:25:47 +11:00
Florent Kermarrec
7a9cf57cfe boards/targets/sim: fix 2016-10-14 17:49:04 +02:00
Robert Jordens
677243bd8c ElasticBuffer: infer reset 2016-10-14 09:43:09 +02:00
Florent Kermarrec
4362e5c528 gen/genlib/cdc: add ElasticBuffer 2016-10-13 17:04:39 +02:00
Florent Kermarrec
b74132f563 boards/platforms: add papilio_pro 2016-09-01 16:27:49 +02:00
Florent Kermarrec
99f2e31b2e soc/tools/remote: allow direct use of comm_udp and some fixes 2016-07-18 17:04:58 +02:00
Florent Kermarrec
d59757eb4a build/xilinx/ise: remove debug print 2016-06-29 23:32:43 +02:00