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4187 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 0c1e1c9769 test/fifo: do not use Record 2015-09-30 17:06:31 +08:00
Sebastien Bourdeauducq b3d5d1628c interconnect/stream: remove param, do not depend on FIFO Record support 2015-09-30 16:40:34 +08:00
Sebastien Bourdeauducq 1b8f313d40 lasmicon: do not depend on FIFO Record support 2015-09-30 16:40:04 +08:00
Sebastien Bourdeauducq 4451bb20e5 genlib/fifo: remove Record support 2015-09-30 16:39:33 +08:00
Sebastien Bourdeauducq c36029fa61 command line options support, CSR CSV, all targets building 2015-09-29 18:14:54 +08:00
Sebastien Bourdeauducq e1927b7cbb flterm: cleanup 2015-09-29 18:14:19 +08:00
Sebastien Bourdeauducq 48b6733c33 cores/gpio: fix import 2015-09-29 18:13:59 +08:00
Sebastien Bourdeauducq 913558ab19 build: stop at the first failed Quartus command 2015-09-29 15:53:18 +08:00
Sebastien Bourdeauducq 5e45b6ced6 build: add missing import for Lattice Diamond 2015-09-29 15:44:57 +08:00
Sebastien Bourdeauducq 6d2d70d879 fhdl/FullMemoryWE: fix clocking 2015-09-29 13:12:27 +08:00
Sebastien Bourdeauducq b4c5ffc1ba fhdl: typecheck ClockSignal and ResetSignal arguments 2015-09-29 13:11:40 +08:00
Sebastien Bourdeauducq dd7dfb0d5e soc_core: simplify settings (assume CPU and CSR present) 2015-09-29 10:19:42 +08:00
Sebastien Bourdeauducq b1a90053f5 minor fixes 2015-09-29 10:19:00 +08:00
Sebastien Bourdeauducq 8e860e3aba Merge branch 'master' of github.com:m-labs/misoc 2015-09-28 20:40:37 +08:00
Sebastien Bourdeauducq 75d927e080 Revert "Sort constants in csr generation." 
This reverts commit d628c147ec.
 2015-09-28 20:40:31 +08:00
Sebastien Bourdeauducq 7c9a7ee757 build: cleanup 2015-09-28 20:34:35 +08:00
Sebastien Bourdeauducq 523377efbe basic out-of-tree build support (OK on PPro) 2015-09-28 20:33:37 +08:00
whitequark bd7748299b Fix typo. 2015-09-28 12:38:58 +03:00
Sebastien Bourdeauducq e92d00f767 move software into misoc 2015-09-28 15:30:19 +08:00
Tim 'mithro' Ansell 27a0e16fea Sort constants in csr generation. 
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.

With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
 CSR=software/include/generated/csr.h
 for i in 1 2 3 4 5 6; do
   rm -f $CSR; python make.py build-headers
   cp $CSR $CSR.$i
 done
 md5sum $CSR.*
```
 2015-09-27 11:05:54 +08:00
Tim 'mithro' Ansell d628c147ec Sort constants in csr generation. 
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.

With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
 CSR=software/include/generated/csr.h
 for i in 1 2 3 4 5 6; do
   rm -f $CSR; python make.py build-headers
   cp $CSR $CSR.$i
 done
 md5sum $CSR.*
```
 2015-09-27 11:04:28 +08:00
Sebastien Bourdeauducq 4fe0f6017c Revert "Use shutil rather then rm -rf command." 
This reverts commit d8fd4fe725.
 2015-09-26 21:55:11 +08:00
Sebastien Bourdeauducq a186bfe0f3 Revert "Use shutil rather then rm -rf command." 
This reverts commit d8fd4fe725.
 2015-09-26 21:54:19 +08:00
Sebastien Bourdeauducq 27b2383607 sdram working on PPro 2015-09-26 21:51:22 +08:00
Sebastien Bourdeauducq 09003a55e1 fhdl/specials/Tristate: handle i=None 2015-09-26 21:49:12 +08:00
Sebastien Bourdeauducq e136352e8f fhdl/structure: relax type requirements for Array elements 2015-09-26 21:47:33 +08:00
Sebastien Bourdeauducq 67133f3542 replace flen with len 2015-09-26 18:50:11 +08:00
Sebastien Bourdeauducq 808cf06add fhdl: replace flen with len 2015-09-26 18:45:10 +08:00
Sebastien Bourdeauducq fa1e8cd822 wrap expressions in Specials 2015-09-26 16:45:13 +08:00
Sebastien Bourdeauducq da425d1bcb add stream, fix CPUs and more imports. simple target boots on ppro. 2015-09-26 16:44:21 +08:00
Sebastien Bourdeauducq 8f42b6f352 fhdl: introduce wrap function 2015-09-26 15:36:28 +08:00
Sebastien Bourdeauducq 67903494bf fhdl: export DUID 2015-09-26 13:46:57 +08:00
Sebastien Bourdeauducq 75ef2f9004 fix most imports 2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq f69674e89c interconnect: add bus/bank components from Migen 2015-09-24 20:48:18 +08:00
Sebastien Bourdeauducq af88a7a3f9 setup: simpler version check, beta status 2015-09-24 16:08:39 +08:00
Sebastien Bourdeauducq ecdc4101b4 lasmicon: enable refresh at all times 2015-09-24 16:01:08 +08:00
Sebastien Bourdeauducq 9b08b037e4 break down sdram, improve consistency of core names 2015-09-24 15:59:55 +08:00
Sebastien Bourdeauducq 0f410e45f1 cores directory 2015-09-24 09:05:10 +08:00
Sebastien Bourdeauducq 83509163df reorganization WIP: flatten core structure (SDRAM still needs to be done) 2015-09-24 00:18:27 +08:00
Sebastien Bourdeauducq 33f344b92a fsm: NextState and NextValue should derive from _Statement 2015-09-23 22:38:10 +08:00
Sebastien Bourdeauducq 8935ca2c9f setup: remove unneeded import 2015-09-23 09:52:24 +08:00
Sebastien Bourdeauducq 01be953e30 setup: cleanup 2015-09-23 09:52:12 +08:00
Sebastien Bourdeauducq 030998658d setup: convert to unix eols 2015-09-23 09:50:31 +08:00
Sebastien Bourdeauducq 74b3e16dd0 CONTRIBUTING.md->rst 2015-09-23 00:57:36 +08:00
Sebastien Bourdeauducq 8421549935 README.md->rst 2015-09-23 00:55:37 +08:00
Sebastien Bourdeauducq 82236d9b40 migen.fhdl.std -> migen 2015-09-23 00:36:47 +08:00
Sebastien Bourdeauducq bd74d39338 misoclib -> misoc 2015-09-23 00:35:02 +08:00
Sebastien Bourdeauducq 8534562185 sim: fix slice assign 2015-09-22 20:33:44 +08:00
Sebastien Bourdeauducq 88f9d72e74 conda: use new branch (revert this after merge) 2015-09-22 17:27:44 +08:00
Sebastien Bourdeauducq 6005548df6 setup.py: cleanup 2015-09-22 17:27:27 +08:00