Charles Papon
|
25eda80fee
|
FpuTest document how to install berkley testfloat
|
2023-03-10 14:46:21 +08:00 |
|
Charles Papon
|
94f19032f0
|
FpuPlugin.access port added
Privileged debug access added
|
2023-03-10 14:44:14 +08:00 |
|
Charles Papon
|
6be1531d36
|
Fpu will not trap anymore on debug access if fs==0
|
2023-03-10 09:17:01 +08:00 |
|
Charles Papon
|
1179c6551f
|
Fix #321 #322 #333 FPU precision removal
|
2023-03-08 16:00:22 +08:00 |
|
Charles Papon
|
f11c642cd6
|
CfuPlugin encoding can now specify cmd/rsp less instruction
|
2023-03-07 16:49:07 +08:00 |
|
Charles Papon
|
3cf8508db1
|
DBus coupled timings improvement
|
2023-03-05 20:31:40 +08:00 |
|
Charles Papon
|
153445ff21
|
Fix CFU / FPU decoder stage fork on illegal instruction
|
2023-03-05 20:29:53 +08:00 |
|
Dolu1990
|
cf70bc6b1f
|
fix last push
|
2023-03-03 14:20:12 +01:00 |
|
Dolu1990
|
b03b00a5c4
|
Improve d$ coupled timings
|
2023-03-03 14:13:51 +01:00 |
|
Dolu1990
|
5493c55ab0
|
Alows Fetcher to have multiple debug injection ports
|
2023-03-03 09:06:20 +01:00 |
|
Dolu1990
|
5f67075e30
|
Fix FPU with F64 support, not removing mantissa precision from F32 #317
|
2023-03-01 13:56:25 +01:00 |
|
Dolu1990
|
6f76a45e7d
|
update mmu test
|
2023-02-23 15:54:39 +01:00 |
|
Dolu1990
|
d7e9c726c3
|
Fix datacache initial flush
|
2023-02-23 14:42:21 +01:00 |
|
Dolu1990
|
c5689e512c
|
CsrPlugin now provide regression args
|
2023-02-23 12:00:25 +01:00 |
|
Dolu1990
|
a40d5f19b2
|
Fix MMU A and D flag handeling
|
2023-02-23 12:00:08 +01:00 |
|
Dolu1990
|
344b2d4eda
|
TestIndividual supervisor missing CSR=yes
|
2023-02-23 11:59:13 +01:00 |
|
Dolu1990
|
9605b663bf
|
D$ now support thightly coupled ram.
Add IBusDBusCachedTightlyCoupledRam plugin
|
2023-02-22 15:26:14 +01:00 |
|
Dolu1990
|
220b599c9a
|
Fix d$ invalidation when the mmu is enabled
|
2023-02-22 13:16:02 +01:00 |
|
Dolu1990
|
15a665af53
|
fix too early
|
2023-02-19 09:51:18 +01:00 |
|
Dolu1990
|
d078297496
|
fix too early
|
2023-02-19 09:48:59 +01:00 |
|
Dolu1990
|
a780eec616
|
Merge branch 'debug-debug' into dev
|
2023-02-13 10:04:41 +01:00 |
|
Dolu1990
|
33e820bdf9
|
FPU now implement a less pessismitic dirty logic
|
2023-02-08 15:16:53 +01:00 |
|
Dolu1990
|
3ae51cdeb8
|
Fix fpu csr access on fs===0 now also trap
|
2023-02-08 14:44:04 +01:00 |
|
Dolu1990
|
692f604dd5
|
Fix VexRiscvSmpClusterGen without linux debug minimal features
|
2023-02-08 11:28:21 +01:00 |
|
Dolu1990
|
cbc89093b3
|
fpu csr access on fs===0 now also trap
|
2023-02-07 10:18:08 +01:00 |
|
Dolu1990
|
9acc5ddc1c
|
Fix FPU access trap on fs = 0 #297
|
2023-02-06 11:44:44 +01:00 |
|
Dolu1990
|
fc9a9d25ed
|
sync
|
2023-02-06 11:43:49 +01:00 |
|
Dolu1990
|
2bc6e70f03
|
Fix RVC decompressor don't care #296
|
2023-01-18 15:19:33 +01:00 |
|
Dolu1990
|
7d3a862183
|
Fix Litex cluster scopt update
|
2023-01-16 18:10:51 +01:00 |
|
Dolu1990
|
aea2e90d1e
|
Upgrade to SBT 1.6.0
|
2023-01-16 17:58:23 +01:00 |
|
Dolu1990
|
773f268f37
|
Fix FPU test syntax
|
2022-12-01 12:04:16 +01:00 |
|
Dolu1990
|
fb084327da
|
Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert
|
2022-11-28 16:30:47 +01:00 |
|
Dolu1990
|
eafeb5fe49
|
Add EmbeddedRiscvJtag.debugCd
|
2022-11-28 11:04:02 +01:00 |
|
Dolu1990
|
a25ae96d33
|
comment debug code
|
2022-11-21 14:02:35 +01:00 |
|
Dolu1990
|
572ca3fcfa
|
Privileged debug fake maskmax to 31
|
2022-11-21 14:01:28 +01:00 |
|
Dolu1990
|
5a8cdee884
|
Fix CsrPlugin dcsr.stepie
|
2022-11-21 11:55:07 +01:00 |
|
Dolu1990
|
4ae7386904
|
Merge pull request #276 from LYWalker/master
Add ability to debug over Intel Virtual JTAG
|
2022-11-18 17:38:50 +01:00 |
|
Dolu1990
|
e19e59b55c
|
Clear mprv on xretAwayFromMachine
|
2022-11-17 15:03:47 +01:00 |
|
Dolu1990
|
663174bc73
|
Privileged debug now implement stoptime stopcount
|
2022-11-17 13:58:29 +01:00 |
|
Dolu1990
|
36c3346e51
|
ensure rvc 0 is detected as a illegal instruction
|
2022-11-17 11:03:45 +01:00 |
|
Dolu1990
|
5e17ab62d6
|
Fix RISC-V debug hardware breakpoints
|
2022-11-14 14:45:11 +01:00 |
|
Dolu1990
|
fe68b8494e
|
Fix a few RISC-V official debug support :
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
|
2022-11-11 14:05:38 +01:00 |
|
Dolu1990
|
2504f9b9b9
|
RISC-V debug havereset implemented
|
2022-11-10 15:49:07 +01:00 |
|
Dolu1990
|
0bfaf06a4a
|
main.cpp add VEXRISCV_JTAG=yes
|
2022-11-10 13:43:14 +01:00 |
|
Dolu1990
|
f71234786f
|
Remove rv64 opcode (shift and lwu)
Thanks Milan
|
2022-10-27 15:44:50 +02:00 |
|
Dolu1990
|
d70794f252
|
fix regression
|
2022-10-27 15:38:34 +02:00 |
|
Dolu1990
|
5d0deb20b3
|
Fix regression compilation
|
2022-10-27 15:20:55 +02:00 |
|
Dolu1990
|
9f6186cd9a
|
Add GenFullWithRiscvPrivilegedDebugJtag demo
|
2022-10-27 14:55:40 +02:00 |
|
Dolu1990
|
6289ebcbe4
|
Merge branch 'riscv-debug' into dev
|
2022-10-27 14:46:46 +02:00 |
|
Dolu1990
|
a6c29766da
|
CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled
|
2022-10-26 15:48:34 +02:00 |