Dolu1990
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3028c19389
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Fix #191 (data cache toAxi bridge)
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2021-07-20 11:20:53 +02:00 |
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Dolu1990
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5f2fcc7d0f
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Merge branch 'dev'
(SpinalHDL 1.6.0)
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2021-07-20 10:39:09 +02:00 |
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Dolu1990
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66bcd7fca7
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readme: add the tom link about JTAG and GDB
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2021-07-20 10:14:54 +02:00 |
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Dolu1990
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0cdad37fff
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VexRiscvSmpClusterGen now implement ebreak
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2021-07-11 21:55:33 +02:00 |
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Dolu1990
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91b3e79485
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SpinalHDL version++
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2021-07-11 21:55:13 +02:00 |
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Dolu1990
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a4c86130cc
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Update README.md
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2021-07-09 09:35:49 +02:00 |
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Dolu1990
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9bc7dce857
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Update README.md
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2021-07-08 09:47:54 +02:00 |
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Dolu1990
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28a75afe7a
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reduce regression time
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2021-07-05 14:17:59 +02:00 |
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Dolu1990
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c79357d1b2
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VexRiscvSmpClusterGen no support atomic less configs
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2021-07-05 12:38:54 +02:00 |
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Dolu1990
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a380c3a36c
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Merge branch 'spinal_1.4.4' into dev
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2021-07-05 11:37:53 +02:00 |
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Dolu1990
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551e76d244
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VexRiscvSmpCluster add a few options
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2021-07-02 19:04:30 +02:00 |
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Dolu1990
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3702ea03c0
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Fix github actions
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2021-06-23 11:48:53 +02:00 |
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Dolu1990
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df7ac05db9
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Update 2.13 compatibility
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2021-06-23 11:48:38 +02:00 |
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Dolu1990
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cdd8a7e94a
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add github action
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2021-06-23 09:04:35 +02:00 |
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Dolu1990
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1017b316b8
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version++
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2021-06-15 15:59:09 +02:00 |
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Dolu1990
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d67fe72de9
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Merge branch 'dev'
# Conflicts:
# build.sbt
# src/test/cpp/regression/main.cpp
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2021-06-15 15:54:13 +02:00 |
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Dolu1990
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1497001ebd
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Update FpuTest with the new rs1/rs2 store mapping
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2021-06-09 13:37:31 +02:00 |
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Dolu1990
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1ee45eeb0a
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More named signals
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2021-06-09 11:27:18 +02:00 |
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Dolu1990
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0e89ebeced
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Improve FPU rs1 timings
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2021-06-09 11:26:58 +02:00 |
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Dolu1990
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e1e1be5797
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exception code can now be bigger than 4 bits
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2021-06-08 12:19:08 +02:00 |
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Dolu1990
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646911a373
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Fix pmp write when there is hazard due to the register file.
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2021-06-07 17:30:47 +02:00 |
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Dolu1990
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87f100dac1
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Merge pull request #174 from lindemer/new_pmp
New PMP plugin optimized for FPGAs
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2021-06-03 20:16:34 +02:00 |
Samuel Lindemer
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156a84e76f
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Fix PMP FSM halting logic
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2021-06-03 13:12:55 +02:00 |
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Samuel Lindemer
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342b06128f
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Combine all the PMP logic into one FSM
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2021-06-02 17:12:10 +02:00 |
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Samuel Lindemer
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2a4ca0b249
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PMP CSR writes occur in execute stage
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2021-06-02 16:01:30 +02:00 |
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Dolu1990
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6cde5f9315
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Better doc about iorange
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2021-06-02 10:27:46 +02:00 |
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Dolu1990
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0272d66971
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Fix CsrPlugin.redoInterface priority
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2021-05-28 16:20:43 +02:00 |
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Samuel Lindemer
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3a4ab7ad51
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Un-pend PMP CSR writes on pipeline flushes
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2021-05-28 16:17:19 +02:00 |
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Samuel Lindemer
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4bdeb7731b
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Merge branch 'new_pmp' of github.com:lindemer/VexRiscv into new_pmp
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2021-05-28 14:00:07 +02:00 |
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Samuel Lindemer
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243d0ec664
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Clarify PMP section in README
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2021-05-28 13:59:59 +02:00 |
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Samuel Lindemer
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d49f8d1b58
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Merge branch 'dev' into new_pmp
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2021-05-28 13:56:15 +02:00 |
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Samuel Lindemer
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24a534acff
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All tests passing on new PMP plugin
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2021-05-28 13:54:55 +02:00 |
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Dolu1990
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4490254d3d
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Csr/Mmu ensure implement that SFENCE_VMA flush the next instructions
SAT flush reworked a bit too
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2021-05-28 13:35:52 +02:00 |
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Samuel Lindemer
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4a2dc0ff5f
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Fix granularity control
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2021-05-27 15:50:45 +02:00 |
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Samuel Lindemer
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6471014131
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Simplify pmpcfg encoding
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2021-05-27 14:34:51 +02:00 |
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Dolu1990
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4b0763b43d
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CsrPlugin.csrMapping now give names to inner signals
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2021-05-27 10:40:55 +02:00 |
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Samuel Lindemer
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a5f66623b7
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Add an "allow" property to individual CSRs
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2021-05-26 16:34:51 +02:00 |
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Samuel Lindemer
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61f68f0729
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Refactor for new CSR API (PMP reads still broken)
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2021-05-26 15:29:27 +02:00 |
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Dolu1990
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6066d8bc26
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CsrPlugin add API to implement CSR in a decoupled way. (very low level api) #174
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2021-05-26 11:44:46 +02:00 |
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Dolu1990
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72328e7bc4
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Arty now has RVC enabled !
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2021-05-25 15:59:02 +02:00 |
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Dolu1990
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2de35e6116
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Merge pull request #184 from allexoll/master
fixed priority of == & != as seemed logical
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2021-05-17 23:42:55 +02:00 |
Alexis Marquet
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8122cc9b5e
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fixed priority of == & != as seemed logical to get less warnings when building
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2021-05-17 18:51:33 +02:00 |
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Dolu1990
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1c3b9e93a2
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Merge pull request #182 from rdolbeau/extra_config
Make the [ID]TLB size configurable from Litex
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2021-05-12 13:54:27 +02:00 |
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Dolu1990
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91195b1a0a
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Merge pull request #181 from pipsoft/master
Improving Documentation on Using BSCANE2 with Murax and OpenOCD
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2021-05-12 13:51:17 +02:00 |
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Dolu1990
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fe739b907a
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Bench DecoderPlugin
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2021-05-10 10:47:15 +02:00 |
Romain Dolbeau
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1bd33a369e
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Make the [ID]TLB size configurable from Litex
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2021-05-08 07:59:34 -04:00 |
Frank Poppen
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5a7c71259d
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Removes PDF and xilinx-xc7.cfg and jtagspi.cfg. Enhances README.md to find in OpenOCD.
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2021-05-06 17:31:40 +02:00 |
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Frank Poppen
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47110a97a3
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Updates two missed issues with nativeJtag documentation from previous commit.
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2021-05-06 08:49:11 +02:00 |
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Frank Poppen
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ac1a6715d7
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Improves the documentation for nativeJtag about Murax with BSCANE2 and OpenOCD.
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2021-05-06 08:44:05 +02:00 |
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Dolu1990
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e78c0546a0
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fix #178
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2021-05-04 21:09:42 +02:00 |