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VexRiscv
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  • bc792a8655 Fix UartRx sim Charles Papon 2017-07-15 19:05:34 +0200
  • 74becb6633 Add VexRiscvAvalon QSysify Charles Papon 2017-07-15 09:41:39 +0200
  • 12d21a08e8 Add DebugPlugin avalon Charles Papon 2017-07-14 19:28:22 +0200
  • d3dcfcec06 Add toAvalon bridge to cached bus Add VexRiscvAvalon demo Charles Papon 2017-07-14 18:04:41 +0200
  • b9cbb27b81 Add Briey informations Charles Papon 2017-07-09 18:02:01 +0200
  • f51f28164a Fix info to flush data cache Briey sim add VGA GUI (SDL2) Add DE0-Nano Briey support Charles Papon 2017-07-09 01:00:46 +0200
  • 8d34c04425 Fix CsrPlugin case issue Better DBusSimplePlugin FMax with catch enables SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing Charles Papon 2017-06-27 19:37:46 +0200
  • e9ab3d71d5 update readme add uart.elf binary for testing Charles Papon 2017-06-26 14:44:52 +0200
  • 4d7455f9c3 add retiming to the dataCache waysHit Add exception catches in the default briey configuration Charles Papon 2017-06-26 14:02:25 +0200
  • e9e7cf9e7a Add briey tracing Better debugPlugin implementation Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing) Add SingleInstructionLimiterPlugin for debug purposes Charles Papon 2017-06-24 14:09:12 +0200
  • edf1b4ed5a Cleaning, better jtag perf Charles Papon 2017-06-18 16:10:27 +0200
  • a94343b98a Update to SpinalHDL 0.10.14 Charles Papon 2017-06-17 15:15:19 +0200
  • c85f6b89de Update verilator requirements Charles Papon 2017-06-15 20:27:20 +0200
  • 03be1f354f Better readme Charles Papon 2017-06-15 14:06:32 +0200
  • bc90331c49 Cleaning Charles Papon 2017-06-15 13:54:34 +0200
  • 88a2c4a603 Cleaning/Add documentation Charles Papon 2017-06-15 13:44:21 +0200
  • 835dd4ad50 Add CSR Charles Papon 2017-06-15 11:16:11 +0200
  • f8678698fc Briey improve AXI FMax Faster debugginPlugin regression Charles Papon 2017-06-11 11:52:59 +0200
  • cbc770deb3 Improve TCP sockets latency Charles Papon 2017-06-10 19:38:42 +0200
  • 9b9d9e2582 Add Uart monitor in the briey testbench Charles Papon 2017-06-10 16:09:14 +0200
  • 11a63491bd Add YAML feature to store CPU info Charles Papon 2017-06-09 16:06:18 +0200
  • 4b9668c063 Remove speed factor overriding when Trace Charles Papon 2017-06-09 08:41:12 +0200
  • f46ec583d6 Briey is now working with DataCache on FPGA Charles Papon 2017-06-07 23:02:21 +0200
  • 8dcf5cf68a Add missing import in Briey testbench Dolu1990 2017-06-07 16:56:29 +0200
  • 8da413dec3 Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK) Add SDRAM Verilator model Charles Papon 2017-06-07 04:19:35 +0200
  • 1e18daecc0 Add ICache and DCache axi bridges functions Add StaticMemoryTranslationPlugin Charles Papon 2017-06-01 17:54:56 +0200
  • ac16558b6b Add haltItByOther Axi4, remove some pipelining Charles Papon 2017-05-30 17:49:29 +0200
  • 6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) Charles Papon 2017-05-29 21:17:14 +0200
  • 213e154b40 Fix regression test debugPlugin bus Charles Papon 2017-05-28 17:41:09 +0200
  • 8dddc7e334 GDB + openOCD successfully connect ! Charles Papon 2017-05-25 13:36:54 +0200
  • 75f6b78daf OpenOCD successfuly connected to target Charles Papon 2017-05-24 23:53:31 +0200
  • 1efed60307 Fix DebugPlugin Add DebugPlugin regression (PASS) Charles Papon 2017-05-22 19:23:11 +0200
  • cc875d1c0b Add TCP server socket to manage debug access from openOCD (as instance) Charles Papon 2017-05-22 00:42:19 +0200
  • 5cda2632df Start implementing debugPlugin test infrastructures Charles Papon 2017-05-21 23:50:40 +0200
  • 9995c5109d move tests Charles Papon 2017-05-21 16:53:48 +0200
  • 6c1d953647 DebugPlugin fully implemented Charles Papon 2017-05-20 18:15:15 +0200
  • 619739d33a preliminary DebugPlugin Charles Papon 2017-05-20 15:16:41 +0200
  • cabf602efc Update README.md Dolu1990 2017-05-19 17:13:33 +0200
  • a5364ad001 Add flush support instruction into the instruction cache Charles Papon 2017-05-19 11:20:33 +0200
  • 736478ff1d CsrPlugin now catch illegal CSR access (wrong address + to low privilege level) Charles Papon 2017-05-09 00:40:44 +0200
  • fe184636dd Improve CsrPlugin FMax Charles Papon 2017-05-08 22:59:05 +0200
  • c69fdf7987 Add basics of the USER mode to CsrPlugin Charles Papon 2017-05-07 23:41:54 +0200
  • 579e93bb5a Rename MachineCsr plugin into CsrPlugin Charles Papon 2017-05-07 22:26:17 +0200
  • 392f3a7d8c Add PrivilegeService (User) (not implemented) Split caches from their plugins file Charles Papon 2017-05-07 20:16:41 +0200
  • a51c27970b Add opcode for clean/invalidate the datacache Change mmu opcodes Charles Papon 2017-05-07 16:02:55 +0200
  • 4d6a6fbb02 Fix Instruction Data cache exceptions Pass all tests including CSR/FreeRTOS Charles Papon 2017-05-07 12:51:47 +0200
  • ca1bc9cf69 DataCache plugin now support all exceptions Charles Papon 2017-05-07 10:44:41 +0200
  • 5ba8ab7947 DataCache add invalidate/clean/invalidateClean on a virtual address/way Charles Papon 2017-05-05 00:43:41 +0200
  • 48a5dc8e79 DCache move the exception bus outside the cache component Charles Papon 2017-05-04 21:01:08 +0200
  • 534a4c3494 mmu working for instruction and data bus (both tested) Charles Papon 2017-05-03 18:42:54 +0200
  • c647ef8bb6 Rework constructors Charles Papon 2017-05-01 20:20:21 +0200
  • 889a040f90 Fix multi port MMU design Change machineCSR to handle exceptions from the writeBack stage Change the DBusCachedPlugin to emit miss exception Charles Papon 2017-05-01 14:29:37 +0200
  • 2ed33106d6 MMU pass simple regression ! Charles Papon 2017-04-29 19:58:17 +0200
  • 227772f19c Add miss files Charles Papon 2017-04-28 16:41:44 +0200
  • 010ba568f0 MMU implemented Datacached using MMU implemented It compile, but nothing is tested Charles Papon 2017-04-28 16:41:23 +0200
  • ba2ca77114 Two stage datacache now pass dhrystone benchmark without error Charles Papon 2017-04-23 23:15:38 +0200
  • 9040326273 WIP two stage DCache, nearly passed the dhrystone benchmark Charles Papon 2017-04-23 18:31:16 +0200
  • e00bf028cb Add HazardPessimisticPlugin for light and very good FMAX hazard tracking Charles Papon 2017-04-17 17:56:47 +0200
  • 024e14ae58 Smaller and faster single stage instruction cache Add fast two stage instruction cache Remove useless address == 0 checks in the HazardPlugin Charles Papon 2017-04-13 18:27:03 +0200
  • c83a157c64 IBusCachedPlugin with twoStage config is now compatible with syncronous regfile Charles Papon 2017-04-09 11:59:09 +0200
  • 9a4c35d7b6 IBusCachedPlugin twoStage config fix Charles Papon 2017-04-08 18:34:44 +0200
  • e3b9e671ec IBusCachedPlugin add two stage cache option for better FMax and better scaling Charles Papon 2017-04-08 17:42:13 +0200
  • 5c594d6d2a IBusCachedPlugin move memory access outside the pipeline Charles Papon 2017-04-07 13:27:47 +0200
  • 8f09867bda Cleaning Charles Papon 2017-04-07 13:09:31 +0200
  • efb27390a7 Better IntAluPlugin Better SrcPlugin Better DBusCachedPlugin Charles Papon 2017-04-06 01:28:52 +0200
  • 2e02a6f0e7 DBusCachedPlugin better write to read hazard logic (FMAX) Add some TODO FMAX comments Charles Papon 2017-04-05 18:37:02 +0200
  • 179e7f7b4c IBusCachedPlugin add asyncTagMemory option Charles Papon 2017-04-05 14:25:11 +0200
  • 2b24cbc8e1 Add pessimistic harzard options Add separated add/sum option in srcPlugin Charles Papon 2017-04-04 00:25:39 +0200
  • acb85a1fb8 Add some decoder comments Charles Papon 2017-04-03 01:33:54 +0200
  • 8ff05bd2a8 Much better decoder using Quine-Mc Cluskey Charles Papon 2017-04-02 21:05:25 +0200
  • a9f7177181 Data cache pass dhrystone benchmark. Data cache todo -> bus error handling Charles Papon 2017-04-01 17:06:59 +0200
  • 2f384364d8 Data cache WIP refractoring Charles Papon 2017-03-31 15:20:51 +0200
  • 26597f78cd cleaning Charles Papon 2017-03-31 11:06:40 +0200
  • 19fe998a52 Instruction cache is now able to catch bus errors Charles Papon 2017-03-30 17:34:24 +0200
  • 95585b4d9a Add instruction cache plugin (tested) Charles Papon 2017-03-30 10:03:53 +0200
  • 32d32845bd Add tests for iRsp, dRsp access faults Charles Papon 2017-03-28 20:25:58 +0200
  • 2cb0e90077 refractoring/cleaning Charles Papon 2017-03-28 01:53:37 +0200
  • 62a55c4cf4 Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions Charles Papon 2017-03-28 01:24:29 +0200
  • eecc1e6b18 Add MachineCsr.mbadaddr logics Charles Papon 2017-03-27 18:35:27 +0200
  • 349d600182 Better readme cleaning Charles Papon 2017-03-27 00:33:34 +0200
  • e5148e5e05 Better readme Charles Papon 2017-03-26 22:43:00 +0200
  • 70e8bc503e Add readme Charles Papon 2017-03-26 22:38:07 +0200
  • 91c52f4e46 Decoder now catch illegal instructions Charles Papon 2017-03-26 18:02:48 +0200
  • c5520656e5 Now able to catch missaligned instruction/data addresses Modify arbitration with an flushAll + isFlushed Charles Papon 2017-03-26 17:20:07 +0200
  • 4000191966 FreeRTOS tested removeIt no more colapse bubbles Charles Papon 2017-03-25 16:44:42 +0100
  • 9bbf3ee3e7 MachineCsr fix csr set/clear with zero MachineCsr pass external/timer interrupts test Charles Papon 2017-03-24 17:40:37 +0100
  • 72d65841d2 MachineCsr pass simple interrupt and exception tests Charles Papon 2017-03-23 23:12:44 +0100
  • ed0660237f MachineCsr wireing/logic done Charles Papon 2017-03-23 01:00:24 +0100
  • de4c2470c8 MachineCsr add mcycle and minstret Charles Papon 2017-03-22 20:38:43 +0100
  • 94770f8e0b Add MachineCsr (untested) Charles Papon 2017-03-22 18:29:34 +0100
  • e9d3977737 Add Arbitration.flushIt Add ExceptionService Add unremovableStage Add MachineCsr (untested) Charles Papon 2017-03-21 18:40:50 +0100
  • c49373f3d1 Fix missing JAL, JALR encoding Charles Papon 2017-03-21 10:29:09 +0100
  • 787682d4f6 Add comments Some refractoring Charles Papon 2017-03-20 14:49:49 +0100
  • 51058f851e Renaming Charles Papon 2017-03-20 12:37:53 +0100
  • ecf853f491 Add Static/Dynamic branch prediction Charles Papon 2017-03-20 12:37:20 +0100
  • d569242124 Add Static branch prediction in decode stage Charles Papon 2017-03-19 23:27:35 +0100
  • 88dee6d2bc Reduce area with reg[0] optimisation Charles Papon 2017-03-18 19:32:54 +0100
  • fc1bb7249a Add trace option to regresion Charles Papon 2017-03-18 14:06:42 +0100
  • 5e9da0f27a Add self checked dhrystone test Charles Papon 2017-03-18 12:32:14 +0100
  • 31db6511dc Fix performance of removed instruction which halt were halting the pipeline Charles Papon 2017-03-18 10:51:55 +0100