eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
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This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
04fc98f834
de0nano/ulx3s: add sdram HalfRate support (untested).
2020-07-24 16:12:46 +02:00
d0ca1befa6
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
2020-07-24 16:11:57 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
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Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
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This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
7cda143250
Allow use of HalfRateGENSDRPHY
2020-07-23 14:41:35 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
02f53e6326
targets/minispartan6: add support for HalfRateGENSDRPHY
2020-07-14 11:01:09 +02:00
d9595a317e
targets/orangecrab: use user_btn as rst_n.
2020-07-06 17:49:05 +02:00
7b1bf9d74a
targets: remove sdcard specific clock domain (now generated by the PHY).
2020-07-03 20:09:30 +02:00
31e6997e70
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
2020-07-01 12:58:48 +02:00
fe3ea805bc
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
2020-06-30 18:44:00 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
fc22e28fe9
targets: replace PCIeSoC with BaseSoC.
2020-06-30 17:41:57 +02:00
d28a0c4258
targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets.
...
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.
2020-06-30 17:37:24 +02:00
e91a5d6b82
targets/pcie: remove soft reset.
2020-06-30 17:28:13 +02:00
1356ebb416
targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
2020-06-29 16:42:53 +02:00
49973990f3
Merge pull request #85 from oskirby/logicbone
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Add Logicbone ECP5 board
2020-06-29 16:24:15 +02:00
76a32ba8ec
Add Logicbone ECP5 board
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The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00
efe33c9764
targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).
2020-06-25 11:21:24 +02:00
6753a92296
targets: add fixed sdcard clock on boards with SDCard support.
2020-06-25 11:20:38 +02:00
04f6d4463a
versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
2020-06-13 11:17:05 +02:00
90092164c8
Add device option for ECP5 Versa board
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Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
b1be5dcc23
Fix FTBFS from undersized BIOS ROM region with Microwatt
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Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
9b45ec0f35
de10lite: simplify vga terminal.
2020-06-11 19:59:32 +02:00
85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
64372d7876
targets/orangecrab: add spi-sdcard and workaround for ValentyUSB.
2020-06-11 19:21:44 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
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Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
45bd50b000
targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e).
2020-06-10 23:14:37 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
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Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
94861bbb9a
targets/orangecrab: uncomment MT41K512M16.
2020-06-10 19:30:07 +02:00
0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support
2020-06-10 03:20:32 +03:00
485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:58 +01:00
f9a8edb973
targets/trellisboard: add initial LiteSDCard support
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-06-03 13:41:57 -04:00
d87a11a9cb
targets/pcie: use generate_litepcie_software on all targets with PCIe.
2020-06-03 08:30:54 +02:00
9f83b6e3cf
targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver.
2020-06-03 08:20:43 +02:00
091ec846a1
targets/acorn_cle_215: automatically copy software from litepcie and generate headers in kernel directory.
2020-06-02 20:09:45 +02:00
06edf48897
targets: rename gateware-toolchain parameter to toolchain.
2020-06-02 13:45:05 +02:00
76df4e39c8
targets: simplify Ethernet/Etherbone integration on targets with both.
2020-05-29 19:20:27 +02:00
2e1a816d1f
pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
2020-05-29 10:41:35 +02:00
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read
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ZCU104: add I2C
2020-05-27 14:56:31 +02:00
e5578a1ae8
zcu104/platform: change I2C number to 0
2020-05-27 14:31:22 +02:00
ac1f1cd6a7
zcu104: add I2C
2020-05-27 12:47:43 +02:00
71f220a24d
colorlight_5a_75b: remove unnecessary parenthesis.
2020-05-27 10:13:44 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
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Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
22f18f618e
pano_logic_g2: move gmii_rst_n to _CRG.
2020-05-26 08:36:06 +02:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
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Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
435913f7d8
platforms/nexys4ddr: add option to build with spi-mode sdcard support
2020-05-24 19:09:25 -04:00
5aeb7d85e6
targets/acorn_cle_215: fix typo in description.
2020-05-21 10:18:06 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
8158d94ae7
targets/c10lprefkit: switch to litehyperbus.
2020-05-19 15:48:19 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
c0b7afc739
targets/alveo_u250: +x.
2020-05-16 11:13:01 +02:00
482d7a6b95
targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations.
2020-05-14 15:34:00 +02:00
2bb7fce5e3
targets/acorn_cle_215: add minimal instructions to reproduce the results.
2020-05-13 17:55:52 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
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[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
c7404e356f
targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury).
2020-05-09 16:39:17 +02:00
d05b10fd76
target/camlink_4k: add missing import.
2020-05-09 12:27:07 +02:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
b9a0f2363c
Merge pull request #74 from tommythorn/master
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targets/orangecrab.py: propagate command arguments
2020-05-08 07:28:05 +02:00
19b12fd984
targets/panol_logic_g2: replace with a minimal target.
2020-05-07 16:36:04 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
27c242b2ca
targets/pcie: switch to PCIe X4 on all boards that support it.
2020-05-07 12:18:39 +02:00
f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
6335717eca
targets/orangecrab.py: propagate command arguments
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The parsed args are stripped off by soc_core_argdict() (called from
soc_sdram_argdict() so we have to pass them explicitly (or pass the
original "args", but this mimics the rest of the code in the repo).
This fixes #72
2020-05-06 18:24:11 -07:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
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Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
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As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
088cceca8b
Add Alveo U250 platform and target
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
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- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
...
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
Florent Kermarrec
rob-ng15
Jędrzej Boczar
Owen Kirby
Raptor Engineering Development Team
Vadim Kaushan
Gabriel Somlo
Skip Hansen
Tommy Thorn
David Shah
Dave Marples
Staf Verhaegen
David Sawatzke