Commit Graph

212 Commits

Author SHA1 Message Date
Leon Schuermann a568b7e26a test_packet.py: test randomly generated headers
Also includes some fixes for the non-last_be test path such that the
expected behavior is the one currently oberserved with the Packetizer
and Depacketizer.
2021-09-10 15:30:05 +02:00
Leon Schuermann 958bcaad2e test_packet.py: add last_be tests 2021-09-10 12:30:04 +02:00
Leon Schuermann 037294dc3b test_packet.py: support passing debug_print parameter 2021-09-09 16:37:26 +02:00
Leon Schuermann 6bda383178 test_packet.py: support {Dep,P}acketizer behavior without last_be 2021-09-09 16:37:26 +02:00
Leon Schuermann a08271b83a test_packet.py: utilize generic stream_inserter/colletor interface 2021-09-09 16:08:12 +02:00
Leon Schuermann ca50cba986 Rewrite test_stream.py with reusable stream_inserter/collector 2021-09-09 16:08:12 +02:00
Florent Kermarrec 79ac09316a interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case. 2021-08-06 16:41:58 +02:00
Florent Kermarrec 1ce48a973b clock/lattice_ecp5: Fix and rework 4-output solver implementation.
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
George Hilliard 8954041a93 clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this.  Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
Florent Kermarrec f6b2135cc9 test/test_timer: Update. 2021-05-27 19:37:51 +02:00
Florent Kermarrec 675349055b inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
Allow supporting all cases.
2021-03-18 13:47:10 +01:00
Blake Smith 98b75d8671 Add initial core test for Timer 2021-01-21 21:37:41 -06:00
Florent Kermarrec f31f9a20f0 boards: remove and switch to litex_boards.
Keeping board definition files directly in LiteX is no longer useful since we are already relying on board
definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards) in various benches/projects
and having definitions files directly in LiteX creates confusion/additional work.

For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards:

from litex.boards.platforms import kc705

from litex_boards.platforms import kc705
2021-01-04 14:09:35 +01:00
Florent Kermarrec 6771ed0796 ci: migrate from Travis CI to Github Actions. 2020-11-24 15:55:49 +01:00
Florent Kermarrec cecb36d608 test/test_clock: update with new supported devices. 2020-11-09 10:37:20 +01:00
Florent Kermarrec e91ec2ed83 soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
With improvements to handle backpressure on non-continous streams.
2020-10-21 09:29:21 +02:00
Florent Kermarrec 305092c7b8 test/test_icap: update. 2020-10-07 12:36:08 +02:00
Florent Kermarrec f7b6dd05ae cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support. 2020-09-03 18:58:10 +02:00
Florent Kermarrec 77ae243310 test: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:40:21 +02:00
Florent Kermarrec a5d0a340c3 test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. 2020-08-04 09:39:23 +02:00
Jędrzej Boczar e78d950a31 soc/interconnect/axi: add AXILite -> AXI converter 2020-07-30 13:50:34 +02:00
Jędrzej Boczar 879e6ffe73 soc/interconnect/axi: add basic AXI Lite up-converter 2020-07-24 13:47:18 +02:00
Jędrzej Boczar 32160e615f soc/interconnect/axi: separate AXI Lite converter channels 2020-07-24 09:25:57 +02:00
Jędrzej Boczar a9d8b81385 test/axi: move all AXI Lite tests to separate file 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 8ae501c391 test/axi: add crossbar stress tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 32d9e212c5 soc/interconnect/axi: improve Timeout module and test it with shared interconnect 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 2cab7fbf0f test/axi: add shared AXI Lite interconnect tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 3a08b21d44 soc/interconnect/axi: implement AXI Lite decoder 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 214cfdcaeb soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to 2020-07-22 17:16:33 +02:00
Jędrzej Boczar baf23c9c9b test/test_axi: add AXI Lite interconnect arbiter tests 2020-07-22 17:16:29 +02:00
Jędrzej Boczar f47ccdae99 soc/interconnect/axi: point-to-point interconnect and timeout module with tests 2020-07-22 17:16:12 +02:00
Florent Kermarrec 47ce15b431 interconnect/wishbone: add minimal UpConverter. 2020-07-21 19:35:14 +02:00
Florent Kermarrec 100aa5a4ca soc/cores/spi/SPIMaster: rewrite/simplify.
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
Jędrzej Boczar 93bcc94b53 soc/interconnect/axi: implement AXILite down-converter 2020-07-16 17:02:49 +02:00
Jędrzej Boczar 78a631f392 test/axi: add AXILite2CSR and AXILiteSRAM tests 2020-07-15 12:40:39 +02:00
Florent Kermarrec 5d202ddb97 test: update. 2020-06-02 13:51:48 +02:00
Florent Kermarrec 80ec5eca76 boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform. 2020-06-02 12:18:12 +02:00
Mariusz Glebocki 7434376c07 test/test_targets: add arty_symbiflow
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:56 +02:00
Florent Kermarrec 3d06dc028c test/test_targets: update build_test. 2020-05-22 08:42:02 +02:00
Pawel Sagan ce49990084 Extend I2S capabilities
This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.

This required to rework the FSM.
2020-05-20 14:31:51 +02:00
Florent Kermarrec 6f8f0d2346 litex_setup: add litehyperbus and remove hyperbus core/test. 2020-05-19 15:49:25 +02:00
Florent Kermarrec 9f941138d2 test/test_targets: workaround to fix travis. 2020-05-13 11:04:40 +02:00
Florent Kermarrec 98d1b45157 platforms/targets: fix CI. 2020-05-05 15:55:09 +02:00
Florent Kermarrec 0b3c4b50fa soc/cores/spi: add optional aligned mode.
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec 4fe31f0760 cores: add External Memory Interface (EMIF) Wishbone bridge.
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
Florent Kermarrec 383fcd36d6 soc/cores/clock: add CycloneVPLL. 2020-04-07 17:24:12 +02:00
Florent Kermarrec 0f17547c5b soc/cores/clock: add initial AlteraClocking/CycloneIV support. 2020-04-07 16:59:53 +02:00
Florent Kermarrec c154d8d2fc test/test_targets: remove versa_ecp3. 2020-03-25 08:47:43 +01:00
Florent Kermarrec f03d862c06 targets: switch to add_ethernet method instead of EthernetSoC. 2020-03-20 23:46:15 +01:00
Florent Kermarrec eb9f54b2bc test: add initial (minimal) test for clock abstraction modules.
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
Florent Kermarrec 54fb3a61cd test/test_targets: use uart-name=stub. 2020-02-29 11:07:10 +01:00
Florent Kermarrec 1d70ef6958 soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) 2020-02-06 17:58:01 +01:00
Florent Kermarrec f58e8188b7 soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 17:00:04 +01:00
Florent Kermarrec f3f9808d1f interconnect/stream: add PipeValid and PipeWait to cut timing paths. 2020-01-29 18:27:29 +01:00
Florent Kermarrec 7b92a17c6e test/test_targets: limit max_sdram_size to 1GB 2020-01-17 13:24:45 +01:00
Florent Kermarrec 68e225fb45 test/test_targets: update 2020-01-15 13:09:03 +01:00
Florent Kermarrec 04017519c8 soc/interconnect/axi: add Wishbone2AXILite 2019-11-20 12:32:22 +01:00
Florent Kermarrec 4b073a440a test/test_axi: cosmetic 2019-11-20 11:22:39 +01:00
Florent Kermarrec 6059712794 test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer 2019-11-16 14:39:18 +01:00
Florent Kermarrec 9642893371 test/test_packet: add randomness on valid input, fix corner-cases on Packetizer 2019-11-16 08:49:04 +01:00
Florent Kermarrec 33c4d961b5 test/test_packet: add 32/64/128-bit loopback tests (passing :)) 2019-11-15 11:37:52 +01:00
Florent Kermarrec 824faf9722 test/test_packet: prepare for testing dw > 8-bit 2019-11-15 11:32:42 +01:00
Florent Kermarrec 442e23d7fd test: add initial test_packet
Use a header with 8,16,32,64,128-bit fields and test a Packetizer/Depacketizer loopback with random field values, random packet data & length.
2019-11-15 10:29:50 +01:00
Florent Kermarrec 650df0ebc2 test/test_targets: skip Minerva test on Travis-CI, remove commented tests 2019-10-28 11:00:08 +01:00
Florent Kermarrec 41ad08e8ef soc/cores/icap: simplify ICAPBitstream (untested) 2019-10-01 21:30:14 +02:00
Florent Kermarrec 63a813af9c soc_core: fix cpu_type=None case and add test for it 2019-09-30 08:26:38 +02:00
Florent Kermarrec 241c3c642b test/test_targets: update cpu-type to mor1kx 2019-09-29 17:12:15 +02:00
Florent Kermarrec 8c080e5fb6 soc/interconnect/csr: add initial field support 2019-09-13 20:01:31 +02:00
Florent Kermarrec 41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
Florent Kermarrec a7895e4982 test/test_axi: remove use of rand_wait, rename rand_level to random 2019-07-23 21:02:09 +02:00
Florent Kermarrec ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Florent Kermarrec 769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
2019-07-13 12:55:19 +02:00
Florent Kermarrec ee8fec10ff soc/cores: add ECC (Error Correcting Code)
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
2019-07-13 11:44:29 +02:00
Florent Kermarrec 4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec 6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec 7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec dc03b7fab9 boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00
Florent Kermarrec c7f36ab08f test: add copyright header 2019-06-23 23:31:11 +02:00
Florent Kermarrec ab1f580470 test/test_axi: remove litex.gen.sim import (was only useful for debug) 2019-06-12 11:28:06 +02:00
Florent Kermarrec 38a2d89a25 test/test_code8b10b: add test_coding 2019-06-10 18:53:30 +02:00
Florent Kermarrec 8fdd5220b3 test/test_prbs: add PRBSGenerator/Checker tests 2019-06-10 16:19:23 +02:00
Florent Kermarrec 55ebcc00eb test/test_targets: add de10lite 2019-06-05 20:03:19 +02:00
Florent Kermarrec b300c32103 test/test_targets: add de2_115, de1soc 2019-06-02 19:22:09 +02:00
Florent Kermarrec 67159349d6 soc/interconnect: remove axi_lite
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
Florent Kermarrec 745d83a332 boards: add initial NeTV2 support (clocks, leds, dram, ethernet) 2019-05-10 18:55:40 +02:00
Florent Kermarrec 3ee9ce0529 test/test_targets: fix test_ulx3s name 2019-05-09 11:48:57 +02:00
Florent Kermarrec 74d37465b3 test/test_targets: comment bad variant tests for now 2019-04-29 17:11:42 +02:00
Florent Kermarrec 5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec 6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Tim 'mithro' Ansell 5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Florent Kermarrec f7c0b118ce test/test_targets: cover all platforms 2019-04-23 11:38:18 +02:00
Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
Florent Kermarrec 28d80bd641 ci: fix test_targets/test_simple 2019-04-22 08:53:43 +02:00
Florent Kermarrec b7f53fb93c test: remove waveforms generation 2019-04-22 08:41:28 +02:00
Florent Kermarrec e98ac680c1 travis: simplify, enable and add RISC-V toolchain to build targets 2019-04-22 08:32:00 +02:00
Florent Kermarrec 9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
Florent Kermarrec ed2578799b test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) 2019-02-27 22:24:56 +01:00
Florent Kermarrec 6a4c133cd2 test: add basic test_csr 2019-02-27 21:46:00 +01:00
Florent Kermarrec 68e1dfca28 boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
Florent Kermarrec 5137c2bf88 test/test_targets: update 2018-11-17 17:36:57 +01:00
Florent Kermarrec a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec 11d536dc4d test: remove test_bitslip (integrated in migen) 2018-11-17 17:29:09 +01:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec e0ce485a17 test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules) 2017-04-25 10:57:34 +02:00
Florent Kermarrec 3ca0cb0cea test: add test_gearbox skeleton 2017-04-24 21:41:46 +02:00
Florent Kermarrec b4ebfb4031 test/test_targets: check top.v generation 2017-04-24 19:25:58 +02:00
Florent Kermarrec 35e3d93d9b test: add basic test_targets.py 2017-04-24 19:13:17 +02:00
Florent Kermarrec dc66dfcb55 test: add test_bitslip (initially in litedram) 2017-04-24 18:50:06 +02:00
Florent Kermarrec 96898f1b39 add test directory with test_code_8b10b.py (from misoc) 2017-04-24 18:46:55 +02:00