125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
01c5051866
liteeth/software: fix wishbone bridge
2015-06-23 01:48:45 +02:00
369cf4c4d7
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
2015-06-23 01:08:49 +02:00
5c939b85ef
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
a3c0e5c4d9
liteeth/core/arp: fix missing MAC address in ARP reply
2015-06-22 23:15:00 +02:00
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
7c2d0fa641
indentation
2015-06-17 08:32:17 -06:00
c0bc94ca1c
soc/sdram: add capability to share L2 cache in multi-CPU SoCs
2015-06-17 15:48:45 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
571ce5791a
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
...
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
1bb2580779
sdram: use new Migen Converter in Minicon frontend and small cleanup
2015-06-02 19:37:08 +02:00
f96a856c97
sdram/phy: fix simphy memory usage
2015-06-02 19:33:09 +02:00
f40140dba5
sdram: refactor minicon and fix issues with DDRx memories
...
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
d50bb8c55e
litesata: more doc fixes
2015-05-26 14:13:13 +08:00
1e47cfce2b
Merge branch 'master' of https://github.com/m-labs/misoc
...
Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst
2015-05-26 13:57:26 +08:00
a9da892b57
litesata: doc fixes
2015-05-26 13:54:31 +08:00
989d8a7c29
liteata: fix spelling & mistakes in doc
2015-05-26 07:37:09 +02:00
eb922f6ddc
litesata: rework frontend doc and add striping, mirroring
2015-05-25 14:04:37 +02:00
0d1a7b9315
litesata: add mirroring
2015-05-25 14:03:14 +02:00
c3716296ae
litesata/examples_designs: add striping
2015-05-25 14:02:02 +02:00
0d2db23603
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
2015-05-25 13:55:15 +02:00
cb053dc011
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
1bb5a05488
litesata: add striping module for use of multiple HDDs.
2015-05-23 14:12:20 +02:00
5daba9af68
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
4d902b578c
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
2015-05-07 20:03:12 +02:00
d9111f6a04
litesata: fix packets figure in frontend doc
2015-05-07 11:06:05 +02:00
5516a49696
litesata: add doc for frontend
2015-05-06 03:57:07 +02:00
6908ddbaf9
litesata: cleanup README/doc
2015-05-06 02:02:22 +02:00
7bdcbc94cd
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
...
Works fine @ 3Gbps, still not working @6.0Gbps
2015-05-06 01:33:02 +02:00
5d5d5edfe2
spiflash: fix miso bitbang with large DQ
2015-05-06 00:05:25 +08:00
553262bcc1
soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
2015-05-04 12:28:49 +02:00
438a0856c5
misoclib/cpu: merge git.py in identifier
2015-05-02 18:42:33 +02:00
da711ad5f1
liteusb: add simple example design with wishbone bridge and software to control it
2015-05-02 18:21:18 +02:00
c98bd9fd79
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
2015-05-02 17:07:58 +02:00
145398d874
liteeth/core/mac: minor cleanup
2015-05-02 16:48:57 +02:00
e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
1761bfba8a
litescope/frontend/wishbone: add support for packetized mode
2015-05-02 16:22:43 +02:00
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
a4617014f4
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
5e649a6577
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
2015-05-01 20:45:04 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
cd3a51ada6
litescope: fix missing source ack on LiteScopeWishboneBridge
2015-05-01 20:44:57 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
23126415d3
litescope: use full name in io.py
2015-05-01 17:49:31 +02:00
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
453279a7c8
litesata: cleanup link
2015-04-27 15:33:01 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
1ef81c4d24
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations
2015-04-27 14:51:03 +02:00
ded3f22574
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)
2015-04-27 14:48:14 +02:00
fe867ccf33
litesata: remove icarus_workaround.patch (obsolete)
2015-04-27 14:44:54 +02:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
ff2d1d9383
litescope: fix read in reg.py
2015-04-20 08:16:31 +02:00
4c0d9f5f36
litescope: remove repeat mode on drivers (not useful) and cleanup
2015-04-18 15:37:38 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
341f635a85
litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design
2015-04-18 13:58:20 +02:00
602eaf69c7
litepcie: fix asciiart in make.py
2015-04-17 14:10:32 +02:00
b4b37fb10e
litepcie: add linux driver + utilities (sysfs + dma)
2015-04-17 13:48:34 +02:00
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
93de581931
soc: add shadow_address parameter
...
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
2015-04-17 13:42:29 +02:00
9666629c4f
soc/cpuif: add with_access_functions parameter
...
When don't necessary need access functions in our csr.h (for example with an X86 CPU)
2015-04-17 13:26:38 +02:00
958f149992
litesata/test: fix PYTHONPATH
2015-04-16 19:49:46 +08:00
2ccb5655c9
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 18:02:26 +02:00
fc68d915c1
global: pep8 (E261, E271)
2015-04-13 17:16:12 +02:00
71d0f6ab2a
global: pep8 (W262)
2015-04-13 17:02:59 +02:00
f3c010c1d5
global: pep8 (E225)
2015-04-13 17:01:05 +02:00
042b160b81
global: pep8 (E222)
2015-04-13 16:58:04 +02:00
01ba965d0c
global: pep8 (E401)
2015-04-13 16:56:25 +02:00
796119fcaf
global: pep8 (E203)
2015-04-13 16:53:07 +02:00
ca7019fa0d
global: pep8 (E231)
2015-04-13 16:51:00 +02:00
9ad90b531e
global: pep8 (E201)
2015-04-13 16:48:51 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
2040727179
litesata: more pep8 (when convenient), should be almost OK
2015-04-13 16:09:04 +02:00
1f19e6ae92
litesata: pep8 (E265)
2015-04-13 15:58:58 +02:00
c8bcbfb855
litesata: pep8 (E261, E271)
2015-04-13 15:51:17 +02:00
2e5501933a
litesata: pep8 (W292)
2015-04-13 15:44:52 +02:00
ea67080462
litesata: pep8 (E225)
2015-04-13 15:44:04 +02:00
Florent Kermarrec
Sebastien Bourdeauducq