91422788ef
actorlib/fifo: do not duplicate safe write logic
2013-09-04 17:33:53 +02:00
523565be63
actorlib/spi/DMAController: use EventSourceProcess
2013-09-04 17:29:42 +02:00
b6eb97e49f
actorlib/spi: add optional irq generation on DMAController
2013-09-04 17:27:57 +02:00
1209ec17f6
actorlib/fifo: rewrite
...
* use classes for less code duplication
* the idea of decorator is to avoid passing common parameters (e.g. clock domain names) in module constructors, so remove those parameters
* style
2013-09-04 17:22:50 +02:00
71b14ac873
actorlib: add fifo
2013-09-04 17:15:22 +02:00
dac10f5570
bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules
2013-08-26 20:33:34 +02:00
2cf6b6c768
wishbone/SRAM: fix non-32-bit bus
2013-08-26 20:32:59 +02:00
33ca4d778f
wishbone2lasmi: configurable data width
2013-08-26 20:29:12 +02:00
628fa8ce9e
wishbone : add DownConverter
2013-08-26 20:28:09 +02:00
a653a6144b
wishbone2lasmi : add support for 32 bits lasmim data width
2013-08-20 18:49:46 +02:00
37930d70ac
genlib/misc: improve genericity of split/displacer/chooser
2013-08-20 18:49:02 +02:00
6f9f08f6eb
add ternary operator sel ? a : b
2013-08-12 13:15:56 +02:00
e12187aa80
add += operator to fragment
2013-08-12 13:15:05 +02:00
fdf022a04b
fhdl: improve naming of related signals
2013-08-08 19:22:17 +02:00
2c580fff03
fhdl/namer: detect leaf nodes better
2013-08-08 12:22:58 +02:00
eb1417c5ed
fhdl: move insert_resets to tools
2013-08-08 11:32:58 +02:00
305c6985bc
fhdl: support for naming related signals
2013-08-08 11:32:37 +02:00
146a1b5d51
namer: add HUID suffix step
2013-08-08 00:15:18 +02:00
fd34b75fb4
namer: split by numbers
2013-08-07 23:22:40 +02:00
0e369318bb
treeviz: support multiline labels
2013-08-07 21:46:03 +02:00
ceddd8afa4
treeviz: improve layout of unbalanced trees
2013-08-07 18:32:02 +02:00
7a243171bd
fhdl/namer: new namer with explicit tree
2013-08-07 17:13:52 +02:00
cc5ff7a772
add tree visualizer
2013-08-07 15:52:35 +02:00
efa7dc9cf4
fhdl/edif: adjust for use with mibuild
2013-08-03 10:54:06 +02:00
7372c7a97c
fhdl/edif: add support for inout signals
2013-08-03 10:51:24 +02:00
0e195da3c0
bank/csrgen: add get_offset function to pre-calculate register addresses
2013-08-02 23:05:54 +02:00
2a296aced7
bank/description/AutoCSR: prefix csr/mem only once
2013-08-02 23:05:21 +02:00
17002fb05e
fhdl: add EDIF back-end
2013-07-31 22:47:43 +02:00
246b860a85
csr: new data width API
2013-07-28 16:33:36 +02:00
6ba0d4bd0d
bus/wishbone: configurable data width
2013-07-27 22:25:07 +02:00
14ed5c1acc
genlib/record: support abstract signal width
2013-07-27 22:18:06 +02:00
7e20320b9d
pytholite/io: len -> flen
2013-07-27 15:38:48 +02:00
04ec60541c
pythloite/ExprCompiler: attempt compile-time evaluation first
2013-07-27 15:38:29 +02:00
f62eff0309
bus/csr/Initiator: correct read latency
2013-07-27 15:37:47 +02:00
e05f520cdf
actorlib/spi: remove unused function
2013-07-27 15:36:42 +02:00
61b8958953
fix synthesis translate on/off switch
2013-07-26 15:55:16 +02:00
9c7ad6b05b
fhdl: RenameClockDomains decorator
2013-07-26 15:42:14 +02:00
cec8fc4ca4
fhdl/specials/Instance: fix item sorting
2013-07-26 14:00:29 +02:00
6e1195415e
genlib/roundrobin: fix n==1 case (correctly)
2013-07-26 09:33:33 +02:00
b8ff2f2792
genlib/roundrobin.py: fix n==1 case
2013-07-26 00:41:08 +02:00
b96eb339af
fhdl: compact Instance syntax
2013-07-25 20:34:19 +02:00
b7ed19c6c5
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
b367932498
fhdl: introduce module decorators
2013-07-25 17:56:31 +02:00
cabae0c32b
genlib: remove direct uses of Fragment
2013-07-24 19:25:14 +02:00
fe18397acc
wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)
2013-07-22 10:30:44 +02:00
5bc9a0b383
fsm.py: set reset_state
2013-07-22 10:30:40 +02:00
411e6ec114
fhdl/tools: do not export resort_statements
2013-07-17 16:50:09 +02:00
d5d2e64dc3
Revert "fhdl/tools/group_by_target: remove resort_statements"
...
This reverts commit 939f01cee2
2013-07-17 16:49:26 +02:00
9190568685
genlib/fifo/AsyncFIFO: fix data corruption bug
2013-07-17 12:10:39 +02:00
939f01cee2
fhdl/tools/group_by_target: remove resort_statements
2013-07-17 10:38:39 +02:00
16ebe41028
fhdl/tools: BUGFIX: fix group_by_target grouping
...
group_by_target does not properly combine target groups if statements
are presented in the order:
({A}, statement1)
({B}, statement2)
({A, B}, statement3)
which returns groups:
({A, B}, [statement1, statement3])
({B}, [statement2])
This patch fixes group_by_target such that the resulting group is:
({A, B}, [statement1, statement2, statement3])
2013-07-17 10:14:39 +02:00
5b36f688ea
Remove ASMI
2013-07-16 18:50:50 +02:00
faa8b7c49a
fhdl/tools: clock domain merging for clock renaming
2013-07-16 18:17:44 +02:00
b016a60b85
lasmibus: fix master locking
2013-07-15 21:45:07 +02:00
7083764b53
genlib/fifo: add test bench
2013-07-15 21:36:39 +02:00
65a0b12812
actorlib/spi/DMAController: export length/storage/trigger
2013-07-13 17:13:15 +02:00
6595b9a111
actorlib/spi/SingleGenerator: export CSRs
2013-07-13 17:12:51 +02:00
c2d6f14087
flow/actor/PipelinedActor: clean up
2013-07-12 18:52:34 +02:00
6aa1e0c199
actorlib/spi/DMAWriteController: len -> flen
2013-07-11 19:22:56 +02:00
f5ddd33e7e
dfi: split phase description
2013-07-10 19:56:47 +02:00
43fe16ef73
bus/lasmibus: add separate req/data ack to target and initiator
2013-07-10 19:09:51 +02:00
af6ef0a3b4
dma_lasmi/Writer: fix default FIFO depth
2013-07-07 20:01:55 +02:00
fa8112c3f5
dma_lasmi/Reader: handle ack=1 when stb=0
2013-07-07 18:57:05 +02:00
7e6fbd31a4
lasmibus/crossbar: simplify master ack generation
2013-07-07 18:56:43 +02:00
b68c00d36f
pytholite: fix kwargs handling
2013-07-03 17:20:05 +02:00
0aa58f5dcf
pytholite: support generator arguments
2013-07-03 16:35:07 +02:00
04efee7847
fhdl: mark variable as deprecated
2013-06-30 20:14:20 +02:00
71b89e4c46
fhdl/verilog: lower complex slices before reset insertion
2013-06-30 14:32:47 +02:00
ded5e569eb
fhdl/tools: separate complex slice lowerer from basic lowerer
2013-06-30 14:32:19 +02:00
9c59ea1e26
genlib/misc: remove bitreverse
2013-06-30 14:31:25 +02:00
a255296171
support re-slicing and non-unit step size
...
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
2013-06-30 14:03:34 +02:00
9d241f8cd3
coding.py: rewrite If() to make verilog more readable
2013-06-30 11:39:47 +02:00
b0d467d744
pytholite: use eval instead of literal_eval
2013-06-28 19:03:55 +02:00
ecc4062071
genlib/coding.py: binary vs. one-hot, priority coding
2013-06-28 15:20:01 +02:00
48a5b86dcd
genlib/cordic: cleanup
2013-06-26 22:46:04 +02:00
080afdc3f9
fhdl/verilog: fix signedness rules for comparison
2013-06-26 22:45:47 +02:00
0224ea01cb
migen/genlib/cordic.py: generic cordic
...
* rotating or vectoring cordic modes
* circular, linear, or hyperbolic functions
* combinatorial, pipelined or iterative evaluation
* arbitrary width, stages and guard bits
* two or four quadrant mode for circular/rotate
2013-06-26 22:31:36 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
b56cb3cefc
fhdl/verilog: improve error reporting
2013-06-24 19:44:25 +02:00
d6f7b4cee6
lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)
2013-06-17 23:36:03 +02:00
5cd0019231
genlib/fifo: support records
2013-06-17 23:35:10 +02:00
6d6d232cad
lasmibus/crossbar: better switching policy
2013-06-15 16:51:09 +02:00
ac2cde0e87
asmibus: remove port sharing
2013-06-14 18:34:36 +02:00
0c52c08989
bus/asmibus: fix slot aging timer
2013-06-14 17:57:43 +02:00
1ec1fb9ebe
bus/lasmibus/Crossbar: support cba_shift=0
2013-06-11 18:15:49 +02:00
fe54c68762
lasmi: fix minor problems
2013-06-10 22:49:33 +02:00
aea3b59432
genlib/fsm: fix handling of zero delayed_enter
2013-06-10 22:49:05 +02:00
3a284b9c1e
actorlib: LASMI DMA (untested)
2013-06-10 22:29:39 +02:00
932bfa7e75
bus: Wishbone -> LASMI bridge (untested)
2013-06-10 18:52:07 +02:00
f2e2397c9d
bus/lasmibus: bugfixes
2013-06-09 23:36:32 +02:00
a836cba790
bus/lasmibus: add target and initiator
2013-06-09 16:03:22 +02:00
35f9f2e9d7
bus/lasmi: interface definition and crossbar (untested)
2013-06-08 15:49:50 +02:00
85813b3b58
csr/sram: fix reads on high addresses when word_bits != 0
2013-06-03 21:52:23 +02:00
e5e3492afe
csr/sram: fix page_bits computation
2013-06-03 21:51:44 +02:00
cebfe787db
genlib/misc: fix import
2013-05-30 18:46:52 +02:00
ebbd5ebcd2
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
2013-05-30 18:45:04 +02:00
f0b0942055
bitreverse: fhdl/tools -> genlib/misc
2013-05-30 18:44:37 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Nina Engelhardt
Nina Engelhardt
Robert Jordens
David Carne
Kenneth Ryerson