Sebastien Bourdeauducq
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4164fb4ac9
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bus/csr: configurable data width
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2012-08-26 21:19:34 +02:00 |
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Sebastien Bourdeauducq
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8de192dfbd
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x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
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Sebastien Bourdeauducq
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b4613d913f
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bus/wishbone: remove use of deprecated multimux
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2012-07-13 17:17:20 +02:00 |
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Sebastien Bourdeauducq
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8062e48697
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bus/asmibus: fix per-port tag generation
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2012-07-12 19:37:50 +02:00 |
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Sebastien Bourdeauducq
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c82a468506
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bus: CSR initiator
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2012-07-07 22:36:15 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
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PureSimulable
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2012-06-12 17:08:56 +02:00 |
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Sebastien Bourdeauducq
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a591510189
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ASMI simulation models
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2012-06-12 16:57:00 +02:00 |
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Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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f061b25a24
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bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
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Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
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Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
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Sebastien Bourdeauducq
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0bea1e2589
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asmi: dat_wm high to disable data write
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2012-05-15 14:41:54 +02:00 |
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Sebastien Bourdeauducq
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f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
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6e3b25ebb6
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
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Sebastien Bourdeauducq
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94b02aa8ed
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bus/asmicon: initiator
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2012-03-30 22:16:31 +02:00 |
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Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
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Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
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92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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Sebastien Bourdeauducq
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c08687b9c6
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bus/dfi: filter signals by direction
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2012-02-15 21:48:05 +01:00 |
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Sebastien Bourdeauducq
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fa9cf3e466
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bus: add DFI
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2012-02-15 18:09:14 +01:00 |
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Sebastien Bourdeauducq
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af5230c8ee
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bus: fix simple interconnect
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2012-02-15 16:42:05 +01:00 |
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Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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46b1f74e98
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bus/asmibus/hub: forward data and tag_call
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2012-02-14 14:00:17 +01:00 |
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Sebastien Bourdeauducq
|
0c214b484e
|
Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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e11d9b9322
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bus/wishbone2asmi: cache hits working
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2012-02-13 23:11:16 +01:00 |
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Sebastien Bourdeauducq
|
264be80f2d
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Fix syntax errors and other stupid problems
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2012-02-13 22:28:02 +01:00 |
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Sebastien Bourdeauducq
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8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
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Sebastien Bourdeauducq
|
060426cb59
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bus/wishbone2asmi: set WM, and send 0 when inactive
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2012-02-13 16:49:43 +01:00 |
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Sebastien Bourdeauducq
|
cad9d3b960
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bus: Wishbone to ASMI caching bridge (untested)
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2012-02-13 16:29:38 +01:00 |
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Sebastien Bourdeauducq
|
7894411418
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bus/asmibus: fix typo
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2012-02-11 20:56:01 +01:00 |
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Sebastien Bourdeauducq
|
ef436a1ec9
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bus/asmibus: add get_slots, fix get_fragment
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2012-02-10 17:49:06 +01:00 |
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Sebastien Bourdeauducq
|
945d655d45
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bus: ASMI hub (untested)
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2012-02-10 15:21:04 +01:00 |
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Sebastien Bourdeauducq
|
47883675db
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bus/wishbone2csr: truncate WB data
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2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
|
a99c2acfa8
|
Remove explicit bus names and rely on the new automatic namer
|
2012-01-27 22:20:57 +01:00 |
|
Sebastien Bourdeauducq
|
076c171c7b
|
Use meaningful class names
|
2012-01-20 23:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
77b3c8e3bb
|
bus: list signals
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2012-01-15 15:48:51 +01:00 |
|
Sebastien Bourdeauducq
|
20425703fa
|
Wishbone: omit fixed LSBs
|
2012-01-13 17:29:05 +01:00 |
|
Sebastien Bourdeauducq
|
566295dea3
|
csr: use optree
|
2011-12-22 19:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
ba40f58491
|
corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
|
2011-12-18 21:47:48 +01:00 |
|
Sebastien Bourdeauducq
|
1a845d4553
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:49 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
929cc98070
|
wishbone2csr: wait for WB deack
|
2011-12-13 17:38:59 +01:00 |
|
Sebastien Bourdeauducq
|
92f24b784d
|
wishbone: decoder: fix slave cyc generation in registered mode
|
2011-12-13 14:08:39 +01:00 |
|
Sebastien Bourdeauducq
|
0ea7a9b2e6
|
wishbone2csr: fix double-write bug
|
2011-12-13 00:25:46 +01:00 |