Florent Kermarrec
|
20207c9c32
|
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
|
2015-03-22 11:11:37 +01:00 |
|
Florent Kermarrec
|
c77562f44b
|
liteusb: make oe_n optional on ft2232h phy
|
2015-03-22 10:56:56 +01:00 |
|
Florent Kermarrec
|
ed5746a1fe
|
liteusb: fix imports
|
2015-03-22 10:56:29 +01:00 |
|
Florent Kermarrec
|
92f81409f2
|
sdram/module: fix tREFI on AS4C16M16
|
2015-03-22 03:20:02 +01:00 |
|
Florent Kermarrec
|
30c2521eb0
|
sdram: pass sdram_controller_settings to SDRAMSoC
|
2015-03-21 23:12:18 +01:00 |
|
Florent Kermarrec
|
70469e1f37
|
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
|
2015-03-21 21:32:39 +01:00 |
|
Florent Kermarrec
|
9bc71f374a
|
rename sdram mapping to main_ram
|
2015-03-21 21:01:46 +01:00 |
|
Florent Kermarrec
|
c55199deb9
|
misoclib/soc: add _integrated_ to cpu options to avoid confusion
|
2015-03-21 20:51:37 +01:00 |
|
Florent Kermarrec
|
c60d99583d
|
sdram/module: add tREFI uniformization to TODO
|
2015-03-21 18:59:16 +01:00 |
|
Florent Kermarrec
|
0f9b0c6f0f
|
sdram/module: add MT47H128M8 DDR2 (used for a customer)
|
2015-03-21 18:52:10 +01:00 |
|
Florent Kermarrec
|
45eb5090db
|
sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
|
2015-03-21 18:41:59 +01:00 |
|
Florent Kermarrec
|
a560ba35bd
|
sdram/module: add AS4C16M16 for minispartan6
|
2015-03-21 18:38:53 +01:00 |
|
Florent Kermarrec
|
854058a8db
|
sdram/module: add description and TODO list
|
2015-03-21 17:44:04 +01:00 |
|
Florent Kermarrec
|
52924ee1f2
|
sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
|
2015-03-21 17:25:36 +01:00 |
|
Florent Kermarrec
|
fd2f8d4bb4
|
sdram: define MT46V32M16 and use it on m1/mixxeo
|
2015-03-21 17:04:58 +01:00 |
|
Florent Kermarrec
|
de2f1c31d5
|
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
|
2015-03-21 16:56:53 +01:00 |
|
Florent Kermarrec
|
6e4b7c6cfd
|
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
|
2015-03-21 12:55:39 +01:00 |
|
Florent Kermarrec
|
9107710f03
|
litexxx cores: use default baudrate of 115200 for all tests
|
2015-03-20 12:22:53 +01:00 |
|
Florent Kermarrec
|
82fe83a1c4
|
sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now)
|
2015-03-19 16:08:03 +01:00 |
|
Florent Kermarrec
|
84b631c929
|
liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
|
2015-03-19 14:52:02 +01:00 |
|
Florent Kermarrec
|
6bdf60567c
|
liteeth/mac/core: fix hw_preamble_crc register generation
|
2015-03-19 13:03:27 +01:00 |
|
Florent Kermarrec
|
236ea0f572
|
liteeth: use bios ip_address in example designs
|
2015-03-18 18:18:43 +01:00 |
|
Florent Kermarrec
|
70f1f96fda
|
litescope/drivers: do not build regs when addrmap is None
|
2015-03-17 16:04:31 +01:00 |
|
Florent Kermarrec
|
a266deb58e
|
LiteXXX cores: fix frequency print in test/test_regs.py
|
2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
|
d2cb41bc63
|
LiteXXX cores: convert port parameter to int if is digit in test/make.py
|
2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
|
2327710387
|
liteeth/phy/gmii : set tx_er to 0 only if it exits
|
2015-03-17 12:24:06 +01:00 |
|
Florent Kermarrec
|
408d0fd2dd
|
liteeth: use default programmer in make.py
|
2015-03-17 12:12:21 +01:00 |
|
Florent Kermarrec
|
ec6ae75065
|
liteeth: use CRG from Migen in base example
|
2015-03-17 12:11:51 +01:00 |
|
Florent Kermarrec
|
a874f85854
|
litescope: use CRG from Migen
|
2015-03-17 11:52:54 +01:00 |
|
Florent Kermarrec
|
faf185d58d
|
liteeth: make gmii phy generic
|
2015-03-16 23:04:37 +01:00 |
|
Florent Kermarrec
|
d8b59c03a2
|
litesata: avoid hack on kc705 platform with new mibuild toolchain management
|
2015-03-14 01:08:36 +01:00 |
|
Florent Kermarrec
|
28d04ec300
|
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
|
2015-03-14 00:49:19 +01:00 |
Sebastien Bourdeauducq
|
32676fffd2
|
soc/sdram: sync with new mibuild toolchain management
|
2015-03-13 23:19:08 +01:00 |
|
Florent Kermarrec
|
c3c7f627d9
|
liteeth/phy: typo (thanks sb)
|
2015-03-12 21:54:10 +01:00 |
|
Florent Kermarrec
|
cd6c04b24f
|
soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
|
2015-03-12 17:12:56 +01:00 |
|
Florent Kermarrec
|
767d45727a
|
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
|
2015-03-12 16:57:38 +01:00 |
|
Florent Kermarrec
|
b157031e8a
|
uart/sim: add pty (optional, to use flterm)
|
2015-03-09 23:29:06 +01:00 |
|
Florent Kermarrec
|
6cbf13036b
|
liteeth/mac: fix padding limit (+1), netboot OK with sim platform
|
2015-03-09 20:59:34 +01:00 |
|
Florent Kermarrec
|
47cceea222
|
liteeth/mac: use Counter in sram and move some logic outside of fsms
|
2015-03-09 20:22:14 +01:00 |
|
Florent Kermarrec
|
b10836a8eb
|
liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
|
2015-03-09 17:21:29 +01:00 |
|
Florent Kermarrec
|
1b58813d13
|
soc: do_exit is now provided by modules
|
2015-03-09 17:18:42 +01:00 |
|
Florent Kermarrec
|
360c849f21
|
liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
|
2015-03-09 13:23:39 +01:00 |
|
Florent Kermarrec
|
5dbd8af4be
|
liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
|
2015-03-09 13:23:37 +01:00 |
|
Florent Kermarrec
|
d20b9c2221
|
uart: pass *args, **kwargs to sim phy
|
2015-03-06 12:08:10 +01:00 |
|
Florent Kermarrec
|
af66ca7bad
|
uart: add phy autodetect function
|
2015-03-06 10:19:29 +01:00 |
|
Florent Kermarrec
|
95fa753149
|
liteeth: add phy autodetect function (phy can still be instanciated directly)
|
2015-03-06 10:10:34 +01:00 |
|
Florent Kermarrec
|
bee8ccf6c7
|
soc: enforce cpu_reset_address to 0 when with_rom is True
|
2015-03-06 08:21:16 +01:00 |
|
Florent Kermarrec
|
2b9397ff5b
|
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
|
2015-03-06 07:56:45 +01:00 |
|
Florent Kermarrec
|
52f1c45407
|
LiteXXX cores: fix test_reg.py
|
2015-03-04 23:13:14 +01:00 |
|
Sebastien Bourdeauducq
|
60e87f6e87
|
Merge branch 'master' of https://github.com/m-labs/misoc
|
2015-03-04 00:46:41 +00:00 |
|
Sebastien Bourdeauducq
|
073641faa1
|
litesata: fix permissions and imports
|
2015-03-04 00:46:24 +00:00 |
|
Florent Kermarrec
|
200791c81d
|
uart: generate ack for rx (serialboot OK with sim)
|
2015-03-04 00:57:37 +01:00 |
|
Florent Kermarrec
|
7c058a52c9
|
com/spi: use .format in tb
|
2015-03-03 10:44:05 +01:00 |
|
Florent Kermarrec
|
1d4dc45436
|
LiteXXX cores: use format in prints
|
2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
|
f27e7a4b22
|
litesata: remove unneeded clock constraint
|
2015-03-03 10:24:05 +01:00 |
|
Florent Kermarrec
|
0bcd6daf63
|
soc: remove is_sim function
|
2015-03-03 10:15:11 +01:00 |
|
Florent Kermarrec
|
905be50451
|
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
|
2015-03-03 09:55:25 +01:00 |
|
Florent Kermarrec
|
9210272356
|
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
|
2015-03-03 09:23:21 +01:00 |
|
Florent Kermarrec
|
2f7206b386
|
sdram: revert use of scalar values for DFIInjector
|
2015-03-03 09:09:54 +01:00 |
|
Florent Kermarrec
|
9df60bf98e
|
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
|
2015-03-03 09:02:53 +01:00 |
|
Sebastien Bourdeauducq
|
ff29c86fe1
|
litesata/kc705: use FMC pin names
|
2015-03-03 01:02:50 +00:00 |
|
Sebastien Bourdeauducq
|
8e48502d03
|
spiflash: style
|
2015-03-03 00:54:30 +00:00 |
|
Florent Kermarrec
|
410a162841
|
sdram: disable by default bandwidth_measurement on lasmicon
|
2015-03-02 19:53:16 +01:00 |
|
Florent Kermarrec
|
473997df26
|
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
|
2015-03-02 16:52:17 +01:00 |
|
Florent Kermarrec
|
8280acd3a7
|
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
|
2015-03-02 12:17:49 +01:00 |
|
Florent Kermarrec
|
3465db25a7
|
soc/sdram: be more generic in naming
|
2015-03-02 11:55:28 +01:00 |
|
Florent Kermarrec
|
97331153e0
|
sdram: create core dir and move lasmicon/minicon in it
|
2015-03-02 11:38:22 +01:00 |
|
Florent Kermarrec
|
de698c51e4
|
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
|
2015-03-02 11:29:43 +01:00 |
|
Florent Kermarrec
|
6b24562eea
|
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
|
2015-03-02 10:59:43 +01:00 |
|
Florent Kermarrec
|
46020fd253
|
sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
|
2015-03-02 10:34:29 +01:00 |
|
Florent Kermarrec
|
c0b38e4905
|
sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
|
2015-03-02 09:18:32 +01:00 |
|
Florent Kermarrec
|
7300879b7f
|
sdram: move dfii to phy
|
2015-03-02 09:08:28 +01:00 |
|
Florent Kermarrec
|
9ad05b21ca
|
sdram: fix remaining data_valid in dma_lasmi
|
2015-03-02 09:05:18 +01:00 |
|
Florent Kermarrec
|
88e7fa21e4
|
sdram: create test dir and move lasmicon/minicon tests to it
|
2015-03-02 08:42:55 +01:00 |
|
Florent Kermarrec
|
b305b7828a
|
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
|
2015-03-02 08:36:39 +01:00 |
|
Florent Kermarrec
|
6d83a112e6
|
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
|
2015-03-01 22:04:27 +01:00 |
|
Florent Kermarrec
|
f58394f6af
|
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
|
2015-03-01 18:25:47 +01:00 |
|
Florent Kermarrec
|
4f37d29d05
|
flash/spi: make bitbang optional (enabled by default)
|
2015-03-01 17:15:22 +01:00 |
|
Florent Kermarrec
|
096e95cb59
|
uart: use data instead of d on endpoint's layouts (coherency with others cores)
|
2015-03-01 16:56:48 +01:00 |
|
Florent Kermarrec
|
1e6d1deae8
|
uart: add sim phy
|
2015-03-01 16:52:50 +01:00 |
|
Florent Kermarrec
|
649cdeb265
|
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
|
2015-03-01 16:48:41 +01:00 |
|
Florent Kermarrec
|
bd4d3cd73b
|
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
|
2015-03-01 12:14:34 +01:00 |
|
Florent Kermarrec
|
9e01bf5fdd
|
litesata: create example design derived from SoC
|
2015-03-01 11:33:38 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
|
liteXXX cores: remove Identifier duplication
|
2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
|
67ca0da1d9
|
liteXXX cores: share same methodology for on-board tests
|
2015-03-01 11:21:12 +01:00 |
|
Florent Kermarrec
|
7b464b2b1c
|
litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
|
2015-03-01 11:03:15 +01:00 |
|
Florent Kermarrec
|
32fce11edf
|
litescope: avoid uart code duplication
|
2015-03-01 10:07:55 +01:00 |
|
Florent Kermarrec
|
1b7f8d0439
|
video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)
|
2015-03-01 10:07:52 +01:00 |
|
Florent Kermarrec
|
144ee7ea9f
|
soc: fix register_rom
|
2015-02-28 23:51:51 +01:00 |
|
Florent Kermarrec
|
b32a0e6f9e
|
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
|
2015-02-28 23:33:00 +01:00 |
|
Florent Kermarrec
|
b34be816ec
|
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
|
2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
|
litescope: create example design derived from SoC that can be used on all targets
|
2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
|
2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
165a5b6760
|
soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
|
2015-02-28 20:04:51 +01:00 |
|
Florent Kermarrec
|
6107b7844a
|
test implementation on all targets and fix issues
|
2015-02-28 12:04:51 +01:00 |
|
Florent Kermarrec
|
1366ff5e26
|
move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
|
2015-02-28 11:51:51 +01:00 |
|
Florent Kermarrec
|
8564b7eb6a
|
soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
|
2015-02-28 11:44:14 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
|
2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
912573f5c9
|
liteusb: move files and modify import to misoclib.com.liteusb
|
2015-02-28 11:18:00 +01:00 |