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192 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 8222ee7f46 framebuffer: use DMA controller from Migen 2013-04-30 18:55:35 +02:00
Sebastien Bourdeauducq 43ac5c8471 Remove undriven reset signals 2013-04-25 20:19:49 +02:00
Sebastien Bourdeauducq 4ff1175dcf Use the Migen asynchronous FIFO 2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq 117b3b8ec7 adc: double-register asynchronous inputs 2013-04-19 12:32:12 +02:00
Werner Almesberger 0dca526a85 milkymist/adc/__init__.py: CounterADC - simple counter-based ADC 
This is a revised version of the counter-based ADC.
 2013-04-19 12:29:17 +02:00
Sebastien Bourdeauducq b018fcedc4 dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time 2013-04-16 22:21:03 +02:00
Sebastien Bourdeauducq 0d21711c1b dvisampler/chansync: use Record.raw_bits() 2013-04-14 17:06:29 +02:00
Sebastien Bourdeauducq 8914969760 dvisampler/clocking: insert DCM_CLKGEN before PLL 2013-04-14 16:53:19 +02:00
Werner Almesberger 7a6e56492c edid.py: sample SCL only every 64 clock cycles, to avoid bouncing 
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).

By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
 2013-04-12 22:48:46 +02:00
Sebastien Bourdeauducq 950d3a4469 framebuffer: use new flow API 2013-04-10 21:34:15 +02:00
Sebastien Bourdeauducq 3be20f6ae4 dfii: adapt to new Record API 2013-04-02 00:15:42 +02:00
Sebastien Bourdeauducq 4f4f260e76 Convert to new CSR API 2013-03-30 17:28:15 +01:00
Sebastien Bourdeauducq caa19f9ab2 framebuffer: larger counters 2013-03-29 17:15:11 +01:00
Sebastien Bourdeauducq 854c0461b4 framebuffer: process two pixels per system clock cycle 2013-03-28 20:46:16 +01:00
Sebastien Bourdeauducq 8fd092ca12 crg: support VGA pixel clock reprogramming 2013-03-28 19:07:17 +01:00
Sebastien Bourdeauducq 1e860c7472 Use new Mibuild generic_platform API 2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq 1045d64e6e framebuffer: RGBA -> ARGB 2013-03-25 18:32:25 +01:00
Sebastien Bourdeauducq 8ee6dab4f9 fb: better ordering of pixels within ASMI words 2013-03-25 15:56:54 +01:00
Sebastien Bourdeauducq 1333367de8 dvisampler: add resolution detection 2013-03-24 00:45:29 +01:00
Sebastien Bourdeauducq ee5bfd4d3d dvisampler/charsync: report position 2013-03-24 00:44:50 +01:00
Sebastien Bourdeauducq 99f9ffa7e8 dvisampler/decoding: set C to 0 during data 2013-03-24 00:44:19 +01:00
Sebastien Bourdeauducq fb9a2788e8 dvisampler/charsync: fix found_control signal 2013-03-24 00:43:22 +01:00
Sebastien Bourdeauducq e06585d9fe dvisampler: clean up EDID data 2013-03-23 13:48:40 +01:00
Sebastien Bourdeauducq 34b8388b45 dvisampler: decode before channel sync 2013-03-22 23:49:25 +01:00
Sebastien Bourdeauducq 037625886d dvisampler: decoding 2013-03-22 21:28:17 +01:00
Sebastien Bourdeauducq d65941d6cc dvisampler: channel synchronization 2013-03-22 18:37:10 +01:00
Sebastien Bourdeauducq 515cdb2bd8 dvisampler: character synchronization 2013-03-21 22:56:13 +01:00
Sebastien Bourdeauducq 7c4ca4fd66 dvisampler/datacapture: deserialize to 10 bits 2013-03-21 19:06:15 +01:00
Sebastien Bourdeauducq fa2331e084 dvisampler/clocking: generate pix reset 2013-03-21 19:02:04 +01:00
Sebastien Bourdeauducq 0a14c3714b dvisampler: software controlled phase detector 2013-03-21 00:46:29 +01:00
Sebastien Bourdeauducq 28cb97068c dvisampler/clocking: proper pix5x reset synchronization 2013-03-18 20:31:59 +01:00
Sebastien Bourdeauducq 5126f616fb dvisampler: use pix5x as IODELAY clock 2013-03-18 19:03:17 +01:00
Sebastien Bourdeauducq 48aae9bee5 Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort 2013-03-18 17:44:01 +01:00
Sebastien Bourdeauducq 74cc045ee1 dvisampler/datacapture: connect IODELAY IOCLK0 2013-03-17 17:42:22 +01:00
Sebastien Bourdeauducq 621526fb7d dvisampler/datacapture: fix tap counter reg 2013-03-17 17:36:49 +01:00
Sebastien Bourdeauducq 3a0cf278fd dvisampler: fixes 2013-03-17 15:41:50 +01:00
Sebastien Bourdeauducq 9f02ced39e dvisampler: add clocking and phase detector 2013-03-17 14:43:10 +01:00
Sebastien Bourdeauducq 0168f83523 MultiReg: remove idomain 2013-03-15 19:51:29 +01:00
Sebastien Bourdeauducq b2173bba9f Use new ClockDomain API 2013-03-15 19:17:05 +01:00
Sebastien Bourdeauducq e99bafe52b dvisampler: add core, EDID support 2013-03-13 19:56:26 +01:00
Sebastien Bourdeauducq a23df42a7a Use automatic register naming 2013-03-12 15:47:54 +01:00
Sebastien Bourdeauducq a9b723568a Use new module, autoreg and eventmanager Migen APIs 2013-03-10 19:32:38 +01:00
Sebastien Bourdeauducq 0caac2246d Use new 'specials' API 2013-02-24 13:07:25 +01:00
Sebastien Bourdeauducq a22ada36d7 corelogic -> genlib 2013-02-24 12:31:00 +01:00
Sebastien Bourdeauducq 5649e88a90 Use Mibuild 2013-02-11 18:23:06 +01:00
Sebastien Bourdeauducq 51f4f920a2 Do not use super() 2012-12-18 14:55:58 +01:00
Sebastien Bourdeauducq c44ff8941c Move Token 2012-12-14 15:54:16 +01:00
Sebastien Bourdeauducq 3986790621 Remove ActorNode 2012-12-12 22:52:55 +01:00
Sebastien Bourdeauducq 053f8ed82c Fix instantiations 2012-12-06 20:57:00 +01:00
Sebastien Bourdeauducq fee70e9866 Use Wishbone SRAM component from Migen 2012-12-01 12:59:32 +01:00
Sebastien Bourdeauducq 293a62dabe Replace Signal(bits_for(... with Signal(max=... 2012-11-29 23:41:51 +01:00
Sebastien Bourdeauducq 8bf6945dfd Use new bitwidth/signedness system 2012-11-29 23:38:04 +01:00
Sebastien Bourdeauducq 7e2bc00c0a Remove Constant 2012-11-28 23:18:53 +01:00
Sebastien Bourdeauducq 79e5f24a65 Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit. 2012-11-28 22:49:22 +01:00
Sebastien Bourdeauducq 0620e75cb8 sram: do not use MemoryPort 2012-11-26 19:32:56 +01:00
Sebastien Bourdeauducq ced98d7bee framebuffer: use new SingleGenerator 2012-10-09 21:11:26 +02:00
Sebastien Bourdeauducq dd6eacba62 Remove uses of the RE signal on field registers 2012-10-09 19:08:37 +02:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Sebastien Bourdeauducq 42d5e850fe framebuffer: disable debugger by default 2012-08-05 01:11:37 +02:00
Sebastien Bourdeauducq a5d6ced181 asmicon: fix and simplify refresh grant logic 2012-08-04 22:59:21 +02:00
Sebastien Bourdeauducq ea4c214790 asmicon/bankmachine: respect SDRAM write-to-precharge specification 2012-08-04 22:49:43 +02:00
Sebastien Bourdeauducq 1451cad710 asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus 2012-08-04 17:38:42 +02:00
Sebastien Bourdeauducq 855eec776d Add ASMIprobe core 2012-08-04 16:31:24 +02:00
Sebastien Bourdeauducq 6807dba8bc asmicon/bankmachine/selector: fix round-robin CE 2012-08-03 22:33:52 +02:00
Sebastien Bourdeauducq df2b653c67 asmicon/bankmachine: do not insert buffer when using _SimpleSelector 2012-08-03 22:11:16 +02:00
Sebastien Bourdeauducq bf8f387324 asmicon: bring full_selector param to top-level 2012-08-03 21:23:54 +02:00
Sebastien Bourdeauducq 0642f0ca94 framebuffer: support df debugger 2012-08-03 18:51:18 +02:00
Sebastien Bourdeauducq 6073f68b69 asmicon: simple selector option 2012-07-13 19:25:38 +02:00
Sebastien Bourdeauducq 768a3a826a x.bv.width -> len(x) 2012-07-13 18:33:03 +02:00
Sebastien Bourdeauducq 809cd99205 asmicon: remove uses of multimux 2012-07-13 18:05:26 +02:00
Sebastien Bourdeauducq 99b889a551 framebuffer: clean shutdown 2012-07-12 20:13:31 +02:00
Sebastien Bourdeauducq 58d1e8a541 framebuffer: use ASMI reader factory 2012-07-12 18:56:17 +02:00
Sebastien Bourdeauducq 73a58977e4 framebuffer: print rgb in simulation 2012-07-07 11:34:22 +02:00
Sebastien Bourdeauducq 99bb705407 framebuffer: fix FIFO read clocking 2012-07-07 11:30:27 +02:00
Sebastien Bourdeauducq 2dfdc8f3c5 Revert "framebuffer: switch to real DMA" 
This reverts commit 3add96212b.
 2012-07-07 10:58:13 +02:00
Sebastien Bourdeauducq 3add96212b framebuffer: switch to real DMA 2012-07-07 00:23:56 +02:00
Sebastien Bourdeauducq ce82f188d0 framebuffer: fix deadlock 2012-07-07 00:12:34 +02:00
Sebastien Bourdeauducq 2b85624924 framebuffer: make simulation easier 2012-07-03 19:04:44 +02:00
Sebastien Bourdeauducq 210e473b5d framebuffer: fix computation of alignment bits 2012-07-03 18:14:39 +02:00
Sebastien Bourdeauducq 59289cfa3b framebuffer: indentation 2012-07-01 22:30:07 +02:00
Sebastien Bourdeauducq e2463da787 framebuffer: fake DMA for testing (WIP) 2012-07-01 21:46:11 +02:00
Sebastien Bourdeauducq fc458a51c9 framebuffer/vtg: fix dataflow control (inc. WA for Migen bug - FIXME) 2012-07-01 21:45:52 +02:00
Sebastien Bourdeauducq 7bf5461ac0 framebuffer: fix pixel split 2012-07-01 21:44:33 +02:00
Sebastien Bourdeauducq 0a29b74cce framebuffer: fix sync generation 2012-07-01 18:43:39 +02:00
Sebastien Bourdeauducq 8ba3118a83 framebuffer: register output of FIFO 2012-07-01 18:13:49 +02:00
Sebastien Bourdeauducq 309124711f framebuffer: video timing generator 2012-07-01 17:03:40 +02:00
Sebastien Bourdeauducq 16c6e4f4a7 framebuffer: FIFO 2012-07-01 15:22:57 +02:00
Sebastien Bourdeauducq acdd34e4ae framebuffer: VTG and FIFO skeleton 2012-06-29 17:09:16 +02:00
Sebastien Bourdeauducq ccbd5e8baf framebuffer: chop memory words 2012-06-29 16:11:05 +02:00
Sebastien Bourdeauducq 0f9e16a034 framebuffer: ala flow->actorlib 2012-06-24 19:15:19 +02:00
Sebastien Bourdeauducq 53fec3191c framebuffer: control.For -> misc.IntSequence 2012-06-22 15:01:25 +02:00
Sebastien Bourdeauducq ef13dc1eb1 framebuffer: address generator and DMA 2012-06-17 18:36:23 +02:00
Sebastien Bourdeauducq a52c3135c1 framebuffer: frame initiator 2012-06-17 17:22:02 +02:00
Sebastien Bourdeauducq 3a02524cc7 VGA framebuffer connections 2012-06-17 13:41:26 +02:00
Sebastien Bourdeauducq f6f42293d1 Clock frequency detection 2012-05-22 13:23:44 +02:00
Sebastien Bourdeauducq 5917048a37 minimac: add tx start register 2012-05-21 22:56:41 +02:00
Sebastien Bourdeauducq 94245517f2 Add timer 2012-05-21 19:46:04 +02:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 79124d822b Identifier 2012-05-17 01:41:41 +02:00