Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,453 Commits 40 Branches 14 Tags 26 MiB
Commit Graph

1453 Commits

Author SHA1 Message Date
Robert Jordens d6c19858fa s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE 2015-04-10 16:12:29 +08:00
Sebastien Bourdeauducq 603a4ef51e liteeth: adapt to new ModuleTransformer 2015-04-10 11:42:25 +08:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Sebastien Bourdeauducq 3a2b677f85 soc,cpuif: support user defined constants 2015-04-09 00:34:36 +08:00
Sebastien Bourdeauducq 8b41ab3a5f make: add target in build names 2015-04-06 23:53:04 +08:00
Sebastien Bourdeauducq 176b9240a9 soc: use new ModuleTransformer API 2015-04-06 23:52:34 +08:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics 
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
 2015-04-04 19:17:24 +08:00
Florent Kermarrec 2583e975f0 soc/cpuif: fix CSR base generation for memories (name is already fullname) 2015-04-03 13:57:37 +02:00
Florent Kermarrec c9c11e7aa8 soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions 2015-04-03 12:45:32 +02:00
Sebastien Bourdeauducq 85b3cced22 use str.format 2015-04-03 17:43:46 +08:00
Sebastien Bourdeauducq c7361f1cdf software/common.mak: fix alignment in quiet output 2015-04-03 17:43:29 +08:00
Florent Kermarrec 0db6e1d624 soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube) 2015-04-03 11:14:28 +02:00
Sebastien Bourdeauducq 875abdeb8d make.py: use os.path.join 2015-04-03 16:00:07 +08:00
Sebastien Bourdeauducq 73d3b8487c crt0-or1k: clean up indentation 2015-04-03 13:23:28 +08:00
Florent Kermarrec b437dc3185 remove use of _r prefix on CSRs 2015-04-02 12:18:43 +02:00
Sebastien Bourdeauducq 696819cc7f move gpio from cpu.peripherals to com 2015-04-02 17:17:33 +08:00
Sebastien Bourdeauducq 63f14f3f30 libbase: implement flush_l2_cache for or1k 2015-04-02 16:47:03 +08:00
Sebastien Bourdeauducq 382ed013af minor cleanups 2015-04-02 14:40:29 +08:00
Sebastien Bourdeauducq bbdbf87599 Merge branch 'master' of github.com:m-labs/misoc 2015-04-02 10:14:24 +08:00
Florent Kermarrec 60124be293 adapt LiteSATA to new SoC 2015-04-01 22:52:19 +02:00
Florent Kermarrec dcdf5df4de adapt LiteEth to new SoC 2015-04-01 22:50:29 +02:00
Florent Kermarrec f65c0a3c95 adapt LiteScope to new SoC 2015-04-01 22:46:24 +02:00
Florent Kermarrec 2d23ab7a85 soc/sdram: fix do_finalize 2015-04-01 22:38:04 +02:00
Sebastien Bourdeauducq 2900429e65 soc: use set 2015-04-02 00:14:56 +08:00
Sebastien Bourdeauducq 369086a178 soc: simplify integrated memory parameters 2015-04-02 00:09:38 +08:00
Sebastien Bourdeauducq 273242b399 soc/sdram: minor cleanup 2015-04-01 23:41:55 +08:00
Sebastien Bourdeauducq 6e2a662dd7 litesata: adapt to new SoC API 2015-04-01 17:37:53 +08:00
Sebastien Bourdeauducq 9599eb6fae soc: remove cpu_boot_file argument 2015-04-01 17:32:45 +08:00
Sebastien Bourdeauducq fb86445d14 soc: remove cpu_or_bridge and with_cpu arguments 2015-04-01 17:29:51 +08:00
Sebastien Bourdeauducq a148af97ba soc: retrieve csr and memory regions using methods 2015-04-01 16:49:32 +08:00
Sebastien Bourdeauducq 8b19a11cd7 soc: use add_wb_master function 2015-04-01 15:56:54 +08:00
Sebastien Bourdeauducq 2a1112b912 soc: simplify/fix csr busword 2015-04-01 15:48:56 +08:00
Sebastien Bourdeauducq 04f29e97e2 soc: remove unnecessary imports 2015-04-01 15:15:09 +08:00
Sebastien Bourdeauducq 5113301130 soc: improve memory region conflict check 2015-04-01 15:14:02 +08:00
Sebastien Bourdeauducq 980791e2b8 soc: remove ns function 2015-04-01 14:33:12 +08:00
Florent Kermarrec b313772a0c sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00
Florent Kermarrec be20fbabe4 soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!) 2015-03-28 23:35:44 +01:00
Florent Kermarrec 0649ded5fd soc: simplify main_ram_size computation and share it between LASMIcon and Minicon 2015-03-28 23:10:33 +01:00
Florent Kermarrec a8d91c0c1d sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue) 2015-03-28 16:35:15 +01:00
Florent Kermarrec 75ee8a5db9 sdram/phy/simphy: OK with DDR3 2015-03-28 01:59:55 +01:00
Florent Kermarrec 51ce7cad6f sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2 2015-03-28 01:18:35 +01:00
Florent Kermarrec a95b3f8f13 sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it) 2015-03-28 01:17:50 +01:00
Florent Kermarrec 7fe748e1b0 sdram/module: clean up tREFI. (use 64ms/8k or 4k) 2015-03-28 01:09:21 +01:00
Sebastien Bourdeauducq 54a88da5b8 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-27 19:22:29 +01:00
Robert Jordens 54c14c7119 pipistrello: add por reset counter 
* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
 2015-03-27 19:18:11 +01:00
Florent Kermarrec f4c35e358e software/bios/sdram: small clean up 2015-03-27 18:24:19 +01:00
Florent Kermarrec 6245dd7b6f software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6 
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
 2015-03-27 16:43:22 +01:00
Florent Kermarrec f85a4f004b software/bios/sdram: add random addressing to memtest 
testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
 2015-03-27 15:49:16 +01:00
Florent Kermarrec 340014dbac targets: revert use of integers in clocks/timings 2015-03-26 23:45:35 +01:00