ecc4c573eb
integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
...
Reported by Florent Kermarrec
2015-10-14 11:09:53 +08:00
e96eba4493
setup: include software and Verilog files
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Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
2015-10-05 12:08:02 +08:00
c38d8175b7
interconnect/stream: add missing part of Demultiplexer
2015-10-05 00:10:55 +02:00
af3723db14
setup: add entry points
2015-10-05 00:45:02 +08:00
5e8c4cc364
setup: fix readme
2015-10-05 00:44:50 +08:00
9c905830dc
sdram: cleanup
2015-10-02 11:37:22 +08:00
d21358fc26
liteeth_mini: fix imports, replace Counter and FlipFlop
2015-09-30 20:17:52 +08:00
617c6ecb47
interconnect/stream: add multiplexer and demultiplexer
2015-09-30 19:43:51 +08:00
b3d5d1628c
interconnect/stream: remove param, do not depend on FIFO Record support
2015-09-30 16:40:34 +08:00
1b8f313d40
lasmicon: do not depend on FIFO Record support
2015-09-30 16:40:04 +08:00
c36029fa61
command line options support, CSR CSV, all targets building
2015-09-29 18:14:54 +08:00
e1927b7cbb
flterm: cleanup
2015-09-29 18:14:19 +08:00
48b6733c33
cores/gpio: fix import
2015-09-29 18:13:59 +08:00
dd7dfb0d5e
soc_core: simplify settings (assume CPU and CSR present)
2015-09-29 10:19:42 +08:00
b1a90053f5
minor fixes
2015-09-29 10:19:00 +08:00
523377efbe
basic out-of-tree build support (OK on PPro)
2015-09-28 20:33:37 +08:00
e92d00f767
move software into misoc
2015-09-28 15:30:19 +08:00
27a0e16fea
Sort constants in csr generation.
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Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.
With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
CSR=software/include/generated/csr.h
for i in 1 2 3 4 5 6; do
rm -f $CSR; python make.py build-headers
cp $CSR $CSR.$i
done
md5sum $CSR.*
```
2015-09-27 11:05:54 +08:00
a186bfe0f3
Revert "Use shutil rather then rm -rf command."
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This reverts commit d8fd4fe725
2015-09-26 21:54:19 +08:00
27b2383607
sdram working on PPro
2015-09-26 21:51:22 +08:00
67133f3542
replace flen with len
2015-09-26 18:50:11 +08:00
da425d1bcb
add stream, fix CPUs and more imports. simple target boots on ppro.
2015-09-26 16:44:21 +08:00
75ef2f9004
fix most imports
2015-09-25 18:43:20 +08:00
f69674e89c
interconnect: add bus/bank components from Migen
2015-09-24 20:48:18 +08:00
ecdc4101b4
lasmicon: enable refresh at all times
2015-09-24 16:01:08 +08:00
9b08b037e4
break down sdram, improve consistency of core names
2015-09-24 15:59:55 +08:00
0f410e45f1
cores directory
2015-09-24 09:05:10 +08:00
83509163df
reorganization WIP: flatten core structure (SDRAM still needs to be done)
2015-09-24 00:18:27 +08:00
01be953e30
setup: cleanup
2015-09-23 09:52:12 +08:00
74b3e16dd0
CONTRIBUTING.md->rst
2015-09-23 00:57:36 +08:00
82236d9b40
migen.fhdl.std -> migen
2015-09-23 00:36:47 +08:00
bd74d39338
misoclib -> misoc
2015-09-23 00:35:02 +08:00
71993edae4
Add init file in sdram/phy dir
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Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory
More info here: https://bitbucket.org/pypa/setuptools/issues/97
2015-09-21 23:46:16 +08:00
b2a4eead0c
uart/software: remove litescope dependency
2015-09-21 09:04:59 +02:00
bc1450e4f2
Adding --help option to flterm.
2015-09-21 11:02:36 +08:00
31956de790
dvisampler/edid: fix sda sampling, needs to be similar to scl.
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Video sources with high scl frequency were not able to access EDID information through I2C.
I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)
2015-09-10 20:51:10 +02:00
12f5858850
Allow installing tools to a prefix.
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(Defaults to /usr/local.)
2015-09-08 08:16:34 -07:00
40f47f447a
create liteethmini and move liteeth to a separate repo ( https://github.com/enjoy-digital/liteeth )
...
LiteEthMini is a subset of LiteEth intended to be used with a CPU and a software stack.
2015-09-08 01:33:57 +02:00
3f5d475b7b
remove litepcie_phy_wrappers submodule
2015-09-07 13:20:16 +02:00
5301a1776d
targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc )
2015-09-07 12:47:40 +02:00
8e8cc8e5a6
move liteusb to a separate repo ( https://github.com/enjoy-digital/liteusb )
2015-09-07 12:44:47 +02:00
e49a3c20c8
move litesata to a separate repo ( https://github.com/enjoy-digital/litesata )
2015-09-07 12:27:40 +02:00
bbeb8a466d
move litescope to a separate repo ( https://github.com/enjoy-digital/litescope )
2015-09-07 12:04:04 +02:00
35e3853f6e
move litepcie to a separate repo ( https://github.com/enjoy-digital/litepcie )
2015-09-07 11:11:43 +02:00
bedf3ed9a6
misoclib/soc: fix add_constant when used for strings
2015-09-01 16:57:50 +02:00
a4808ace6f
litecores: remove unneeded AutoCSR inheritance in example designs (thanks William D. Jones)
2015-08-26 22:36:48 +02:00
e91ce85cfd
litescope/core/port: fix missing self.comb...
2015-08-24 20:12:39 +02:00
27b1dd7d9e
litescope/core/port: fix EdgeDetector CSRs names
2015-08-24 19:40:53 +02:00
fd31e6ae61
litescope/core/port: fix LiteScopeEdgeDetector (refactoring issues)
2015-08-24 18:23:38 +02:00
f3d68a54d5
liteth/phy: simplify clk_freq in LiteEthPHY autodetect function (thanks Sebastien)
2015-08-22 16:30:42 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Tim 'mithro' Ansell
Rohit Kumar Singh