Hardware/VexRiscv
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865 commits

Author SHA1 Message Date
Marcus Comstedt
6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990
4ece59385d DataCache split redo / refilling execute stage halt 2020-10-19 18:12:20 +02:00
Dolu1990
ec55187033 improve LightShifterPlugin arbitration halt timings 2020-10-09 11:37:48 +02:00
Dolu1990
bbaa0520c0
Fix UserInterruptPlugin interrupt enable 2020-10-09 10:45:23 +02:00
bunnie
72f85ef6c0 Merge remote-tracking branch 'origin/dev' into dev-asid 2020-10-04 19:53:29 +08:00
bunnie
65e6f6054b Add ASID field to SATP 
ASID field is missing from the SATP which causes compatibility
issues with Xous.

While this patch resolves the Xous issue, it has not been tested
on Linux.
 2020-10-04 15:34:58 +08:00
Dolu1990
98de02051e
Merge pull request #135 from zeldin/bigendian 
Add support for big endian byte ordering
 2020-10-01 16:43:00 +02:00
Dolu1990
3f5e771a5c dbus mmu access improvement 2020-09-17 22:06:29 +02:00
Dolu1990
de820daf74 add earlyBranch option to Smp config 2020-09-13 18:33:06 +02:00
Dolu1990
49488d19af pipeline data cache unaligned access check 2020-09-07 12:01:11 +02:00
Marcus Comstedt
8e466dd13c Add support for RV32E in RegFilePlugin 
The RV32E extension removes registers x16-x31 from the ISA.  This
is useful when compiling with -mem2reg to save on BRAMs.  On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.

Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
 2020-09-06 17:05:31 +02:00
Dolu1990
4c3cad97d3 fix CfuPlugin generation 2020-09-04 10:36:12 +02:00
Marcus Comstedt
c489143442 Add support for big endian byte ordering 2020-08-30 15:17:09 +02:00
Dolu1990
7dcaa0c390 VexRiscvSmpCluster now avoid useless decoder for plic/clint 2020-08-13 11:26:11 +02:00
Dolu1990
69d5ba239a Smp config now initialise regfile using logic 2020-07-28 16:15:17 +02:00
Dolu1990
cc423cbe49 Litex cluster add DMA sel feature 2020-07-21 19:42:27 +02:00
Dolu1990
15bda15bc9 Litex cluster can now set cache layout 2020-07-21 19:35:56 +02:00
Dolu1990
9f62f37538 improve LitexCluster area for single core configuration 2020-07-21 15:45:02 +02:00
Dolu1990
da666ade49 Add VexRiscvLitexSmpClusterCmdGen 2020-07-21 15:07:32 +02:00
Dolu1990
fe5401f835 BmbGenerators refractoring (bus -> ctrl) 2020-07-16 13:04:25 +02:00
Dolu1990
da73317912 Cleanup BmbGenerators 2020-07-15 20:51:46 +02:00
Dolu1990
5f0aec7570 BmbInterconnectGenerator refractoring 2020-07-15 17:03:05 +02:00
Dolu1990
d0a572de98 Add openroad config 2020-07-08 01:37:10 +02:00
Dolu1990
32f778613f DBusCachedPlugin now support asyncTagMemory 2020-07-08 01:36:58 +02:00
Dolu1990
60ee7e2b4c Better VexRiscvSmpCluster config 2020-07-08 01:36:40 +02:00
Dolu1990
51070d0e69 Fix MmuPlugin when used in multi stage config 2020-07-05 13:17:39 +02:00
Dolu1990
06584518da Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck 2020-07-05 13:17:07 +02:00
Dolu1990
a404078117 Few fixes 2020-07-05 13:16:39 +02:00
Dolu1990
c51e25f8c4 Litex SoC add coherent DMA master 2020-07-05 13:15:44 +02:00
Dolu1990
32539dfe6d Got VexRiscvSmpLitexCluster refractoring to work 2020-06-30 22:29:33 +02:00
Dolu1990
0da94ac66f Bring back smp cluster parameters 2020-06-29 15:49:01 +02:00
Dolu1990
062509deee Update Bmb brides and comment out SmpCluster for now 2020-06-29 11:44:10 +02:00
Dolu1990
c12f9a378d Fix inv regression 2020-06-20 13:18:46 +02:00
Dolu1990
f0f2cf61da D$ inv/ack are now fragment, which ease serialisation of wider invalidations 2020-06-19 15:57:56 +02:00
Dolu1990
c18bc12cb2 Fix DebugPlugin.fromBmb 2020-06-19 15:57:21 +02:00
Dolu1990
490c1f6b02 cleanup of old todo 2020-06-19 15:56:45 +02:00
Dolu1990
b0cd88c462 SmpCluster now with proper jtag and plic 2020-06-12 16:18:41 +02:00
Dolu1990
cb5597818d Fix d$ generation crash 2020-06-07 11:29:07 +02:00
Dolu1990
1f9fce6388 Fix d$ uncached writes exception handeling 2020-06-06 22:12:37 +02:00
Dolu1990
760d2f74d0 Update litex cluster to implement utime 2020-06-05 13:31:24 +02:00
Dolu1990
d6455817e7 smp cluster now have 2w*4KB of d$ , no more rdtime emulation 2020-06-05 10:43:03 +02:00
Dolu1990
71760ea372 CsrPlugin now support utime csr to avoid emulation 2020-06-05 10:43:03 +02:00
Dolu1990
3dafe8708b Cfu update 2020-06-05 10:43:03 +02:00
Dolu1990
0668046407 More smp cluster profiling 2020-06-05 10:40:51 +02:00
Dolu1990
97c2dc270c Fix typo 2020-06-04 10:11:30 +02:00
Dolu1990
89c13bedbd Fix litex smp cluster sim 2020-06-03 16:31:54 +02:00
Dolu1990
73f88e47cb Fix BmbToLitexDram coherency 2020-06-03 16:31:54 +02:00
Dolu1990
db50f04653 Add litexMpCluster 2020-06-03 16:31:54 +02:00
Dolu1990
08189ee907 DebugPlugin now support Bmb 2020-06-02 19:13:55 +02:00
Dolu1990
2942d0652a fix Briey verilator 2020-06-01 11:18:25 +02:00
Dolu1990
5e5c730959 Add LitexSmpDevCluster with per cpu dedicated litedram ports 2020-05-29 10:56:55 +02:00
Dolu1990
bc4a2c3747 Fix SmpCluster jtag 2020-05-27 14:19:37 +02:00
Dolu1990
18cce053a3 Improve SingleInstructionLimiterPlugin to also include fetch stages 2020-05-27 14:19:17 +02:00
Dolu1990
a64fd9cf3b Add CsrPlugin external hartid 
d$ rsp/sync now decrement pendings by signal amount
 2020-05-20 13:49:10 +02:00
Tom Verbeure
b901651ab5 Add default value of NONE to uinstret CSR. 2020-05-19 14:48:35 -07:00
Tom Verbeure
c74b03b4de Add uinstret support. 2020-05-19 13:40:46 -07:00
Dolu1990
cf60989ae1 Litex smp cluster now blackboxify d$ data ram 2020-05-14 00:05:54 +02:00
Dolu1990
42fef8bbcd Smp cluster now use i$ reduceBankWidth 2020-05-12 23:59:38 +02:00
Dolu1990
685c914227 Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width 2020-05-12 23:59:38 +02:00
Dolu1990
0471c7ad76 Fix machineCsr test 2020-05-12 23:55:47 +02:00
Dolu1990
cb44a474fc more smp cluster profiling 2020-05-12 13:25:55 +02:00
Dolu1990
63511b19a2 smp cluster add more profiling 2020-05-11 10:35:24 +02:00
Charles Papon
b592b0bff8 Add regression TRACE_SPORADIC, LINUX_SOC_SMP 
regression golden model now properly sync dut exceptions
 2020-05-09 17:00:13 +02:00
Dolu1990
0a159f06b2 update smp config 2020-05-07 22:50:36 +02:00
Dolu1990
0e76cf9ac8 i$ now support multi cycle MMU 2020-05-07 22:50:25 +02:00
Dolu1990
41ee8fd226 MmuPlugin now support multiple stages, D$ can now take advantage of that 2020-05-07 13:37:53 +02:00
Dolu1990
8e025aeeaa more litex smp cluster pipelining 2020-05-07 13:18:11 +02:00
Dolu1990
fc0f3a2020 cleanup mmu interface 2020-05-06 18:05:20 +02:00
Dolu1990
6323caf265 MMU now allow $ to match tag against tlb pyhsical values directly 
D$ retiming
D$ directTlbHit feature added for better timings
 2020-05-06 17:09:46 +02:00
Dolu1990
ed4a89e4af more pipelineing in Litex SMP cluster interconnect 2020-05-06 17:06:45 +02:00
Dolu1990
8043feebd5 More VexRiscv smp cluster probes 2020-05-06 17:06:17 +02:00
Dolu1990
09724e907b play around with CSR synthesis impact on design size 2020-05-05 00:32:59 +02:00
Dolu1990
c16f2ed787 Add probes in SmpCluster sim 2020-05-04 12:54:28 +02:00
Dolu1990
b0f7f37ac8 D$ now support memDataWidth > 32 2020-05-04 12:54:16 +02:00
Dolu1990
93b386e16e litex smp cluster now use OO decoder 2020-05-02 23:44:58 +02:00
Dolu1990
f0745eb0d9 update SMP line size to 64 bytes 2020-05-02 23:44:27 +02:00
Dolu1990
09ac23b78f Fix SMP fence lock when 4 stages CPU 2020-05-01 12:45:16 +02:00
Dolu1990
f5f30615ba Got litex SMP cluster to work on FPGA 2020-05-01 11:14:52 +02:00
Dolu1990
dc0da9662a Update SMP fence (final) 2020-05-01 11:14:11 +02:00
Dolu1990
7c50fa6d55 SmpCluster now use i$ line of 64 bytes 2020-04-29 14:03:00 +02:00
Dolu1990
9e9d28bfa6 d$ now implement consistancy hazard by using writeback redo 2020-04-29 14:02:41 +02:00
Dolu1990
86e0cbc1f3 I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage 2020-04-29 13:59:43 +02:00
Dolu1990
7b80e1fc30 Set SMP workspace to use i$ memDataWidth of 128 bits 2020-04-28 22:11:41 +02:00
Dolu1990
eee9927baf IBusCachedPlugin now support memory data width multiple of 32 2020-04-28 22:10:56 +02:00
Dolu1990
03a0445775 Fix SMP for configuration without writeback stage. 
Include SMP core into the single core tests regressions
 2020-04-28 15:50:20 +02:00
Dolu1990
4a49b23636 Fix regression 2020-04-28 14:38:27 +02:00
Dolu1990
3ba509931c Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax 2020-04-27 17:38:06 +02:00
Dolu1990
5fd0b220cd CsrPlugin add openSbi config 2020-04-27 17:37:30 +02:00
Dolu1990
0c59dd9ed3 SMP fence now ensure ordering for all kinds of memory transfers 2020-04-27 17:37:15 +02:00
Dolu1990
3fb123a64a fix withStall 2020-04-21 21:20:54 +02:00
Dolu1990
3885e52bb7 Merge remote-tracking branch 'origin/dev' into smp 2020-04-21 17:21:48 +02:00
Dolu1990
056bf63866 Add more consistancy tests 2020-04-21 16:03:03 +02:00
Dolu1990
b389878d23 Add smp consistency check, fix VexRiscv invalidation read during write hazard logic 2020-04-21 12:18:10 +02:00
Dolu1990
0e55caacab deduplicae VexRiscv wishbone 2020-04-21 10:33:51 +02:00
Dolu1990
b383b4b98b Add commented usage of fromXilinxBscane2 2020-04-20 12:13:12 +02:00
Dolu1990
8e8b64feaa Got full linux / buildroot to boot in 4 cpu config 2020-04-19 19:49:26 +02:00
Dolu1990
a1b6353d6b workaround AMO LR/SC consistancy issue, but that need a proper fix 2020-04-19 19:48:57 +02:00
Dolu1990
ad2d2e411a Add tap less debug plugin bridges 2020-04-19 17:56:33 +02:00
Dolu1990
af128ec9eb revert to 4 cpu 2020-04-18 01:27:35 +02:00
Dolu1990
4a49e6d91f initialize the clint in sim 2020-04-18 01:26:31 +02:00