Hardware/VexRiscv
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Author SHA1 Message Date
Dolu1990
805bd56077 Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value 2021-07-30 16:51:07 +02:00
Dolu1990
671bd30953 Update Bmb invalidate/sync parameters 2021-07-28 13:44:04 +02:00
Dolu1990
ba8f5f966a Vfu typo 2021-07-26 15:27:20 +02:00
Dolu1990
b717f228d6 VfuPlugin wip 2021-07-26 15:17:06 +02:00
Dolu1990
c242744d02 CfuPlugin now only fork when the rest of the pipeline is hazard free 2021-07-26 14:45:54 +02:00
Dolu1990
f3f9b79f9a VexRiscvSmpCluster earlyShifterInjection added 2021-07-21 18:34:57 +02:00
Dolu1990
3028c19389 Fix #191 (data cache toAxi bridge) 2021-07-20 11:20:53 +02:00
Dolu1990
66bcd7fca7 readme: add the tom link about JTAG and GDB 2021-07-20 10:14:54 +02:00
Dolu1990
0cdad37fff VexRiscvSmpClusterGen now implement ebreak 2021-07-11 21:55:33 +02:00
Dolu1990
91b3e79485 SpinalHDL version++ 2021-07-11 21:55:13 +02:00
Dolu1990
9bc7dce857
Update README.md 2021-07-08 09:47:54 +02:00
Dolu1990
28a75afe7a reduce regression time 2021-07-05 14:17:59 +02:00
Dolu1990
c79357d1b2 VexRiscvSmpClusterGen no support atomic less configs 2021-07-05 12:38:54 +02:00
Dolu1990
a380c3a36c Merge branch 'spinal_1.4.4' into dev 2021-07-05 11:37:53 +02:00
Dolu1990
551e76d244 VexRiscvSmpCluster add a few options 2021-07-02 19:04:30 +02:00
Dolu1990
3702ea03c0 Fix github actions 2021-06-23 11:48:53 +02:00
Dolu1990
df7ac05db9 Update 2.13 compatibility 2021-06-23 11:48:38 +02:00
Dolu1990
cdd8a7e94a add github action 2021-06-23 09:04:35 +02:00
Dolu1990
1017b316b8 version++ 2021-06-15 15:59:09 +02:00
Dolu1990
1497001ebd Update FpuTest with the new rs1/rs2 store mapping 2021-06-09 13:37:31 +02:00
Dolu1990
1ee45eeb0a More named signals 2021-06-09 11:27:18 +02:00
Dolu1990
0e89ebeced Improve FPU rs1 timings 2021-06-09 11:26:58 +02:00
Dolu1990
e1e1be5797 exception code can now be bigger than 4 bits 2021-06-08 12:19:08 +02:00
Dolu1990
646911a373 Fix pmp write when there is hazard due to the register file. 2021-06-07 17:30:47 +02:00
Dolu1990
87f100dac1
Merge pull request #174 from lindemer/new_pmp 
New PMP plugin optimized for FPGAs
 2021-06-03 20:16:34 +02:00
Samuel Lindemer
156a84e76f Fix PMP FSM halting logic 2021-06-03 13:12:55 +02:00
Samuel Lindemer
342b06128f Combine all the PMP logic into one FSM 2021-06-02 17:12:10 +02:00
Samuel Lindemer
2a4ca0b249 PMP CSR writes occur in execute stage 2021-06-02 16:01:30 +02:00
Dolu1990
6cde5f9315 Better doc about iorange 2021-06-02 10:27:46 +02:00
Dolu1990
0272d66971 Fix CsrPlugin.redoInterface priority 2021-05-28 16:20:43 +02:00
Samuel Lindemer
3a4ab7ad51 Un-pend PMP CSR writes on pipeline flushes 2021-05-28 16:17:19 +02:00
Samuel Lindemer
4bdeb7731b Merge branch 'new_pmp' of github.com:lindemer/VexRiscv into new_pmp 2021-05-28 14:00:07 +02:00
Samuel Lindemer
243d0ec664 Clarify PMP section in README 2021-05-28 13:59:59 +02:00
Samuel Lindemer
d49f8d1b58
Merge branch 'dev' into new_pmp 2021-05-28 13:56:15 +02:00
Samuel Lindemer
24a534acff All tests passing on new PMP plugin 2021-05-28 13:54:55 +02:00
Dolu1990
4490254d3d Csr/Mmu ensure implement that SFENCE_VMA flush the next instructions 
SAT flush reworked a bit too
 2021-05-28 13:35:52 +02:00
Samuel Lindemer
4a2dc0ff5f Fix granularity control 2021-05-27 15:50:45 +02:00
Samuel Lindemer
6471014131 Simplify pmpcfg encoding 2021-05-27 14:34:51 +02:00
Dolu1990
4b0763b43d CsrPlugin.csrMapping now give names to inner signals 2021-05-27 10:40:55 +02:00
Samuel Lindemer
a5f66623b7 Add an "allow" property to individual CSRs 2021-05-26 16:34:51 +02:00
Samuel Lindemer
61f68f0729 Refactor for new CSR API (PMP reads still broken) 2021-05-26 15:29:27 +02:00
Dolu1990
6066d8bc26 CsrPlugin add API to implement CSR in a decoupled way. (very low level api) #174 2021-05-26 11:44:46 +02:00
Dolu1990
72328e7bc4 Arty now has RVC enabled ! 2021-05-25 15:59:02 +02:00
Dolu1990
1c3b9e93a2
Merge pull request #182 from rdolbeau/extra_config 
Make the [ID]TLB size configurable from Litex
 2021-05-12 13:54:27 +02:00
Dolu1990
fe739b907a Bench DecoderPlugin 2021-05-10 10:47:15 +02:00
Romain Dolbeau
1bd33a369e Make the [ID]TLB size configurable from Litex 2021-05-08 07:59:34 -04:00
Dolu1990
e78c0546a0 fix #178 2021-05-04 21:09:42 +02:00
Dolu1990
fa2899a1a2 Merge branch 'debugPlugin' into dev 2021-04-26 11:11:38 +02:00
Dolu1990
45e67ccf56 sync 2021-04-26 11:10:55 +02:00
Dolu1990
0a0998fcea #176 fix typo 2021-04-22 14:02:46 +02:00