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Author SHA1 Message Date
Florent Kermarrec
df92e2aea7 tools/litex_json2dts: switch VexRiscv to SMP, update SDCard dts. 2020-12-21 16:11:32 +01:00
enjoy-digital
0a9c9562dc
Merge pull request #738 from antmicro/quartus-handle-includes 
Quartus: handle vh and svh files
 2020-12-21 10:19:27 +01:00
Florent Kermarrec
90b9f4eca3 soc/interconnect/axi: fix AXIInterface.get_ios(). 2020-12-21 08:51:04 +01:00
Karol Gugala
7f6af0a437 Quartus: handle vh and svh files 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2020-12-20 11:53:08 +01:00
enjoy-digital
7fccf9fcd0
Merge pull request #736 from Disasm/ecpdap 
Add ECPDAP programmer
 2020-12-18 15:39:24 +01:00
Florent Kermarrec
b7aec66929 soc/interconnect/axi: simplify AXI Full connect_to_pads and get_ios. 2020-12-18 15:35:04 +01:00
enjoy-digital
57d9816065
Merge pull request #734 from antmicro/axi4-slave-bridge 
Add get_ios for full AXI and add missing signals in connect_to_pads
 2020-12-18 15:25:54 +01:00
enjoy-digital
9ae5a4f4ea
Merge pull request #735 from Dolu1990/vexriscv_smp 
cores/cpu/vexriscv_smp add AES support
 2020-12-18 14:43:04 +01:00
enjoy-digital
f055b1be69
Merge pull request #732 from Disasm/ecp5-compress 
Add option for ECP5 bistream compression
 2020-12-18 14:42:34 +01:00
Vadim Kaushan
0fe2477f69
Add ECPDAP programmer 2020-12-18 15:42:18 +03:00
Dolu1990
ee47c7b260 cores/cpu/vexriscv_smp add AES support 2020-12-18 12:10:33 +01:00
Piotr Binkowski
f26769eb4d interconnect/axi: add connect_to_pads to full AXI 2020-12-18 09:06:45 +01:00
Piotr Binkowski
18e90234b0 interconnect/axi: add get_ios to full AXI 2020-12-18 08:59:11 +01:00
Vadim Kaushan
2bc76f3245
Add option for ECP5 bistream compression 2020-12-18 00:21:05 +03:00
Florent Kermarrec
4092180662 tools/lxterm/json: json file provide relative path, add json file directory to image names. 
Allow sharing same json file between serial boot and Ethernet/SDCard/SATAboot:

boot.json:
{
	"Image":        "0x40000000",
	"rv32.dtb":     "0x40ef0000",
	"rootfs.cpio":  "0x41000000",
	"opensbi.bin":  "0x40f00000"
}

If boot.json and images are located in images directory, using lxterm --images=images/boot.json
will now work.
 2020-12-17 16:08:32 +01:00
enjoy-digital
f777cddefe
Merge pull request #731 from lindemer/pmp 
Allow selection of VexRiscv_Secure* from lxsim CLI
 2020-12-14 19:41:51 +01:00
Samuel Lindemer
c23a894014 Allow selection of VexRiscv_Secure* from lxsim CLI 2020-12-14 10:54:02 +01:00
Florent Kermarrec
bc2b7995f5 integration/export/get_csr_header: don't generate replace/write fields access functions when CSR is read only. 2020-12-14 10:51:37 +01:00
bunnie
649edd189a
Merge pull request #729 from betrusted-io/master 
another minor change - reveal STARTUPE2 block's ring oscillator
 2020-12-13 02:19:56 +08:00
bunnie
422cc2baae another minor change - reveal STARTUPE2 block's ring oscillator 2020-12-13 01:49:43 +08:00
Florent Kermarrec
fb3b09db15 integration/soc/add_uart: add crossover+bridge support. 
Useful to have both CPU UART and bridge debug capability.
 2020-12-10 18:32:21 +01:00
Florent Kermarrec
88bd754dd6 software: add minimal baremetal demo app. 
Used to demonstrates how to easily create baremetal apps, boot to it with LiteX and
also ease litex_term testing.

To build it: export BUILD_DIR=xxyy/litex/litex/boards/targets/build/arty && make
To load it: lxterm /dev/ttyUSB1 --kernel=demo.bin

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading demo.bin to 0x40000000 (9264 bytes)...
[LXTERM] Upload complete (9.8KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x40000000

--============= Liftoff! ===============--

LiteX minimal demo app built Dec 10 2020 17:13:02

Available commands:
help               - Show this command
reboot             - Reboot CPU
led                - Led demo
donut              - Spinning Donut demo
litex-demo-app> led
Led demo...
Counter mode...
Shift mode...
Dance mode...
litex-demo-app> donut
Donut demo...

                                      $$$$$@@@@@
                                  $##########$$$$$$$$
                               ###*!!!!!!!!!***##$$$$$$
                             ***!!====;;;;===!!**###$$$$#
                            **!===;;;:::::;:===!!**####$##
                          !*!!==;;:~-,,.,-~::;;=!!**#######!
                          !!!!=;:~-,.......-~::==!!***#####*
                         !!!!==;~~-.........,-:;==!!***###**!
                         !**!!=;:~-...     ..-:;=!!!********!
                        ;!*#####*!!;.       ~:;==!!!******!!=
                        :!*###$$$$#*!      :;==!!!!!****!!!=;
                        ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=;
                         ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~
                         -;!*###$$$$$$$###******!!!!!!!===;~
                          -;!!*####$#####******!!!!!!==;;:-
                           ,:=!!!!**#**#***!!!!!!!====;:~,
                             -:==!!!*!!*!!!!!!!===;;;:~-
                               .~:;;========;=;;:::~-,
                                  .--~~::::~:~~--,.
litex-demo-app>
 2020-12-10 17:16:28 +01:00
bunnie
ef6fd57613
Merge pull request #727 from betrusted-io/master 
fix a timing error in the S7 OPI block
 2020-12-10 23:17:29 +08:00
Florent Kermarrec
ee41fbb338 tools: deprecate litex_jtag_uart (now directly integrated in litex_term). 2020-12-10 15:48:10 +01:00
bunnie
8ee0fdbf8e fix a timing error in the S7 OPI block 
should have no impact on normal operation, the path is
only for registering addresses that are correlated with
ECC errors as reported by the OPI device.
 2020-12-10 22:48:09 +08:00
Florent Kermarrec
39b84581f4 tools/litex_term: add JTAG UART support (litex_term jtag_uart). 2020-12-10 15:46:12 +01:00
Florent Kermarrec
384041affb tools/litex_term/crossover: use burst to speed up reads. 2020-12-10 14:34:00 +01:00
Florent Kermarrec
48dc574703 integration/soc/add_uart: pass fifo_depth to UARTCrossover. 2020-12-10 14:33:29 +01:00
Florent Kermarrec
1976fd4b90 tools: deprecate litex_crossover_uart (now directly integrated in litex_term). 2020-12-10 13:54:21 +01:00
Florent Kermarrec
feeb2f72e0 tools/litex_term: add direct crossover UART bridge suppport (lxterm --crossover) and switch to multiprocessing. 2020-12-10 13:45:38 +01:00
Stéphane Gourichon
8a82ddf6e1
CSR fields: generate convenience functions (#725) 
Generate convenience methods to extract/replace bits in CSR fields, only generate replace if CSR register is writable.
 2020-12-10 11:32:21 +01:00
Florent Kermarrec
cd80c87f1a software/liblitedram/write_leveling: revert ideal_delay to 0, ensure write delay is set just before 0 to 1 transition. 2020-12-09 19:51:19 +01:00
Florent Kermarrec
5ebea9434b software/liblitedram/sdram: improve comments. 2020-12-09 17:53:33 +01:00
enjoy-digital
44d21cb0f3
Merge pull request #722 from geertu/master 
tools/litex_json2dts: Miscellaneous fixes and improvements
 2020-12-08 14:01:14 +01:00
enjoy-digital
a80398d2ab
Merge pull request #724 from sergachev/master 
soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too
 2020-12-08 13:45:12 +01:00
Florent Kermarrec
c6fb9ef939 software/liblitedram: limit clk/cmd scan to 1/2 tCK. 
Restrict the clk/cmd scan to 1/2 tCK since the full scan is not required
and in some cases can compromise the calibration with the wrong best clk/cmd
value selection.

This should also allow using cmd_latency=0 in all cases.
 2020-12-08 10:01:18 +01:00
Florent Kermarrec
c19c343ecf software/libbase: add memtest_access before testing bus/addr/data to exit early if bus errors are detected. 2020-12-07 14:05:51 +01:00
Florent Kermarrec
fb05fbc5cc software: always provide flush_l2_cache implementation (even if empty) to avoid #ifdefs CONFIG_L2_SIZE. 2020-12-07 13:45:05 +01:00
Florent Kermarrec
3ce74f6e29 software/libbase/memtest: cosmetic cleanups. 2020-12-07 13:23:58 +01:00
Ilia Sergachev
9af9ee6b66 soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too 2020-12-06 00:23:30 +01:00
Florent Kermarrec
bed072ef19 tools/litex_term: use different payload_length/delay settings for USB-ACM. 2020-12-04 19:59:49 +01:00
Geert Uytterhoeven
d8b844bbda tools/litex_json2dts: Group tuples in liteeth reg property 
To improve human readability and enable automatic validation, the tuples
in "reg" properties should be grouped using angle brackets.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-12-04 16:38:48 +01:00
Geert Uytterhoeven
a17b535906 tools/litex_json2dts: Fix DTS indentation 
Make indentation of the generated DTS more consistent, by always using 8
spaces (no TABs), and aligning continued lines.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-12-04 16:21:52 +01:00
Geert Uytterhoeven
8265d06728 tools/litex_json2dts: Fix SPI bus #size-cells 
As per Documentation/devicetree/bindings/spi/spi-controller.yaml,
"#size-cells" must be zero for a PCI bus.

This gets rid of the following build warnings:

    build/orangecrab/orangecrab.dts:105.29-39: Warning (reg_format): /soc/spi@f0004800/mmc-slot@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
    buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
    buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
    buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
    buildroot/rv32.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
    build/orangecrab/orangecrab.dts:91.46-110.19: Warning (spi_bus_bridge): /soc/spi@f0004800: incorrect #size-cells for SPI bus
    buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
    buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'

Fixes: fafa844aa7 ("json2dts: Add Linux DT generation script")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-12-04 16:19:29 +01:00
Florent Kermarrec
b7c0922ec1 tools/litex_term: increase outstanding to 128 (4 is slowing down speed with USB-FIFO). 2020-12-04 16:01:35 +01:00
Florent Kermarrec
894802d131 tools/litex_term: add sfl_outstanding parameter (set to 4), cleanup code and increase inter-frame delay. 
This fixes upload on OrangeCrab with USB-ACM, but we still need to understand why
sfl_payload_length can't be set to 255 with USB-FIFO.
 2020-12-04 15:46:18 +01:00
Florent Kermarrec
5e10552f3f soc/interconnect/packet/Packetizer: fix last_be for 10gbe. 2020-12-03 17:11:04 +01:00
enjoy-digital
168c5380cf
Merge pull request #718 from trabucayre/zynq_fix_constraints 
don't add pins without pad location in constraints file
 2020-12-03 16:21:06 +01:00
enjoy-digital
88023394fd
Merge pull request #721 from daveshah1/dave/nexus-pll-resetena 
clock/lattice_nx: Set PLLRESET_ENA parameter
 2020-12-03 15:54:16 +01:00
Florent Kermarrec
dba6653cb4 tools/litex_term: reduce sfl_payload_length to 64 as before. 
See: https://github.com/enjoy-digital/litex/issues/720.
 2020-12-03 12:52:00 +01:00
David Shah
90315868a8 clock/lattice_nx: Set PLLRESET_ENA parameter 
If this parameter isn't set to ENABLED; then the PLLRESET signal is
ignored.

Signed-off-by: David Shah <dave@ds0.me>
 2020-12-03 11:49:48 +00:00
Florent Kermarrec
172dc18dfb bios/boot: remove SFL_CMD_LOAD_NO_CRC support (non longer useful since CRC checking is now fast). 2020-12-03 12:11:48 +01:00
enjoy-digital
136db6a0ca
Merge pull request #719 from davidlattimore/no-error-recovery 
lxterm: Speed up CRC checked uploads
 2020-12-03 12:06:46 +01:00
Florent Kermarrec
d6a49e85c4 integration/soc_core: only add IRQs from interrupt_map if SoC supports them. 2020-12-03 09:48:42 +01:00
Florent Kermarrec
42e7b8d35a integration/soc/irq: improve error message. 2020-12-03 09:47:50 +01:00
David Lattimore
b421d50b40 lxterm: Increase maximum payload size to match BIOS 
sfl_frame (in sfl.h) already had a payload size of 255.

This should give about a 10% speed gain due to reduced overhead. 8 bytes
of header per 251 bytes sent, as opposed to 8 bytes of header per 60
bytes sent
 2020-12-03 13:44:09 +11:00
David Lattimore
03c2257baf lxterm: Deprecate --no-crc flag 
The flag is left, in case people are using it from scripts, but now does
nothing besides printing a warning.
 2020-12-03 13:37:43 +11:00
David Lattimore
513a799a39 lxterm: Don't attempt to recover from CRC errors during upload. 
This allows transfers to proceed at the full speed of the serial link.
We still check all responses, but will now fail outright if a CRC error
occurs.
 2020-12-03 13:37:26 +11:00
Gwenhael Goavec-Merou
b896b20e46 don't add pins without pad location in constraints file 2020-12-02 13:24:15 +01:00
Florent Kermarrec
8eecbd7b57 integration/soc/add_sdcard: integrate interrupts. 2020-12-01 13:25:05 +01:00
Gabriel Somlo
5cc3db0176 soc: cosmetic: reduce horizontal indentation in IRQ init. 2020-11-30 16:29:16 -05:00
Gabriel Somlo
9af56cf247 soc: fix typo in IRQ handler exception 2020-11-30 16:27:31 -05:00
Florent Kermarrec
d193092e16 cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle. 2020-11-30 12:18:59 +01:00
Florent Kermarrec
18f66a79f2 cores/cpu/zynq7000: improve methods to pass provide/pass configuration to PS7. 
User can now only use set_ps7 and provides the .xci file, preset file or/and additional configuration:

To use a .xci file, in the design do:
self.cpu.set_ps7(xci="ps7.xci")

To use a preset:
self.cpu.set_ps7(preset="preset_name")

To use a config dict:
self.cpu.set_ps7(name="ps7_name", config={"param0": "0", "param1": "1"})

It's also possible to use preset and then pass and additionnal config dict:
self.cpu.set_ps7(preset="preset_name")
self.cpu.add_ps7_config({"param0": "0", "param1": "1"})
or all at once:
self.cpu.set_ps7(preset="preset_name", config={"param0": "0", "param1": "1"})
 2020-11-30 11:30:48 +01:00
enjoy-digital
30e8773819
Merge pull request #711 from trabucayre/ps7_config 
zynq7000: add tcl to create zynq IP based on board preset and custom configuration
 2020-11-30 10:28:54 +01:00
Florent Kermarrec
c8fcaaea2d integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt"). 2020-11-30 10:17:03 +01:00
Florent Kermarrec
146068b048 integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled. 
This prevents adding peripherals that requires IRQ support to SoC not supporting
them. Enabling is done automatically when a CPU with interrupt support is added,
but this can also be added manually.
 2020-11-30 10:06:45 +01:00
gsomlo
d9f9b4aeb6
Merge pull request #713 from daveshah1/dave/rocket-reset-fix 
rocket: Fix UB due to optimised away DFFs
 2020-11-28 08:12:33 -05:00
David Shah
61895bef37 rocket: Fix UB due to optimised away DFFs 
As both clock and async reset for the debug DFFs were 0, and there was
no initial value on them, they were being validly optimised away by
newer Yosys versions to 1'bx which was propagating into and breaking the
core.

This fixes the problem by tying the async resets to the CPU reset
signal.

Signed-off-by: David Shah <dave@ds0.me>
 2020-11-28 11:15:42 +00:00
Florent Kermarrec
c491c60b7d soc/cores/prbs/PRBSRX: add pause signal to pause errors counting. 
Simplify CDC when passing the errors to software by allowing the values to stabilized.
 2020-11-28 11:33:57 +01:00
Florent Kermarrec
869e50ade8 soc/cores/prbs: minor cosmetic cleanups. 2020-11-28 10:27:22 +01:00
Florent Kermarrec
e2dcdcf917 build/lattice/programmer/load_bitstream: convert .bit to .svf with bit_to_svf it bitstream_file provided as .bit. 2020-11-28 08:58:57 +01:00
Florent Kermarrec
289234b102 build/lattice: add bit_to_svf script from Project Trellis to allow using OpenOCD with Diamond. 2020-11-28 08:58:04 +01:00
Gwenhael Goavec-Merou
08b6d0388c zynq7000: add tcl to create zynq IP based on board preset and custom configuration 2020-11-28 08:56:47 +01:00
Florent Kermarrec
785bc7e86c build/lattice/diamond: set timingstrict default value to False (similar to others build backends) 2020-11-28 07:56:30 +01:00
Florent Kermarrec
e5a7375b30 cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset. 
It seems EHXPLLL does not loose locked when reseted.
 2020-11-26 18:56:24 +01:00
Florent Kermarrec
b02753ecfa tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices. 
litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234
Etherbone scan on 192.168.1.x network:
- 192.168.1.20
- 192.168.1.50
 2020-11-26 13:33:20 +01:00
Florent Kermarrec
4a748a53b8 soc/interconnect/packet: add initial PacketFIFO. 
For now just ensures that we have a full packet in the FIFO before setting source.valid.
It would be nice in the future to also be able to discard packets in the FIFO.
 2020-11-26 11:27:42 +01:00
Florent Kermarrec
c3660379db tools/remote/comm_udp: probe Etherbone server on open(). 2020-11-26 09:06:52 +01:00
Florent Kermarrec
f390161baa integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel. 2020-11-26 09:06:06 +01:00
enjoy-digital
896d1ba988
Merge pull request #709 from daveshah1/oxide-build 
Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX
 2020-11-25 19:21:11 +01:00
Florent Kermarrec
ad62e15d98 tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie. 2020-11-25 16:25:31 +01:00
Florent Kermarrec
595c6738a3 tools/remote/etherbone: speed up encoding/decoding. 2020-11-25 16:08:12 +01:00
Florent Kermarrec
3d2574a488 tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts. 
This way, user scripts can be use RemoteClient (communicating with the Server that has
already been opened on the right interface) or directly use CommXY in the scripts.

Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between
the client and server). On fixed configuration using CommXY directly can then be faster
and also avoid manual opening of the server.
 2020-11-25 15:05:28 +01:00
Florent Kermarrec
2c3687983c tools/litex_server/client: cleanup. 2020-11-25 11:34:12 +01:00
Florent Kermarrec
fa9149720f tools/remote/comm_udp: keep up to date with new encoding/decoding. 2020-11-25 11:33:44 +01:00
Florent Kermarrec
c003293b31 tools/remote/etherbone: simplify/speed up decoding. 2020-11-25 11:33:02 +01:00
David Shah
c0822bac1a Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-25 09:44:51 +00:00
Florent Kermarrec
01e75addff tools/remove/etherbone: simplify/speed up encoding. 2020-11-25 10:00:28 +01:00
Florent Kermarrec
2a1df9beeb tools/remote/etherbone: replace merge_bytes with direct call to int.from_bytes. 2020-11-25 09:11:33 +01:00
Florent Kermarrec
4d5dca2d74 tools/remote/etherbone: replace split_bytes by direct call to int.to_bytes. 2020-11-25 09:07:58 +01:00
Florent Kermarrec
9b696373a2 tools/remove/etherbone: cosmetic cleanup, add assert for maximum burst size (255). 2020-11-25 08:53:11 +01:00
Robert Winkler
6684e7ae7a symbiflow: restore add_false_path_constraint 
Restore the method to fix SymbiflowToolchain class API

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-11-24 15:34:32 +01:00
Florent Kermarrec
f918d0bf02 tools/remove: add 0x to hex debug prints. 2020-11-24 14:06:46 +01:00
Florent Kermarrec
cddf19df98 integration/soc/add_etherbone: expose buffer_depth. 2020-11-23 17:50:31 +01:00
enjoy-digital
a1bfa79092
Merge pull request #705 from betrusted-io/reset-docs 
correct the documentation for the ctrl reset register
 2020-11-23 17:46:50 +01:00
bunnie
119062c068
Merge pull request #706 from betrusted-io/master 
add a hook for activating the GSR inside the STARTUPE2 block for spi_opi
 2020-11-24 00:29:14 +08:00
bunnie
33f073a0a9 add a hook for activating the GSR inside the STARTUPE2 block for spi_opi 2020-11-24 00:27:18 +08:00
bunnie
4d7fe81a07 correct the documentation for the ctrl reset register 2020-11-24 00:19:05 +08:00
Alessandro Comodi
0431af729c symbiflow: remove workarounds for symbiflow 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-11-23 10:33:11 +01:00
bunnie
8e39060d26
Merge pull request #701 from enjoy-digital/csr_eventmanager_cleanup 
interconnect/csr/EventManager: simpifly/cleanup code that documents C…
 2020-11-20 03:24:09 +08:00
Florent Kermarrec
32989c17b6 soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME. 2020-11-18 22:04:14 +01:00
enjoy-digital
1ac34bf5bf
Merge pull request #702 from antmicro/fix-disable-build-timestamp 
litex: soc: do not add the timestamp in the BIOS if it was disabled
 2020-11-18 22:01:25 +01:00
Florent Kermarrec
9440975a1f cores/ram: cosmetic cleanup. 2020-11-18 21:52:43 +01:00
Alessandro Comodi
3c0d41781f litex: soc: do not add the timestamp in the BIOS if it was disabled 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-11-18 17:36:50 +01:00
Florent Kermarrec
444a605dea build/xilinx: fix build with LITEX_ENV_VIVADO/LITEX_ENV_ISE set by user. 2020-11-18 15:40:15 +01:00
Florent Kermarrec
ee1ea9baab bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect. 2020-11-18 15:13:57 +01:00
Florent Kermarrec
470b6873ca interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation. 
A read_only mode has been added to CSRStatus to allow enabling writes on pending register and get the written
data used to clear events.
 2020-11-18 13:06:55 +01:00
Florent Kermarrec
30b2f187f4 soc/integration/builder: add generate_doc parameter and --doc args to builder_args. 
This allows generating the documentation easily from target files with --doc.
 2020-11-18 11:37:47 +01:00
enjoy-digital
b8b6fe2165
Merge pull request #699 from betrusted-io/document_events 
Create EventManager option for documented bits
 2020-11-18 11:06:04 +01:00
Leon Schuermann
778afb45d2 Add SoC timer peripheral timer-uptime CLI parameter 
This allows enabling the uptime register in the timer core from the
command line.
 2020-11-17 23:29:11 +01:00
Jędrzej Boczar
3bd5d6cc0e software/liblitedram: fix issues with command/write delays not being incremented. 2020-11-17 16:26:37 +01:00
bunnie
10256aa109 resolve xobs review comments 2020-11-17 05:10:16 +08:00
bunnie
377794748b add API to turn on documentation in I2S block for interrupts 2020-11-17 04:55:46 +08:00
bunnie
3dc18efe70 make documented events optional 2020-11-15 23:18:46 +08:00
bunnie
5d6c851f32 try to fix issue with unnamed sources 2020-11-15 22:03:23 +08:00
bunnie
ea80e9ef32 improve documentation strings, try to handle unnamed events better 2020-11-15 21:50:26 +08:00
bunnie
6a0a896e96 improve documentation output 2020-11-15 17:07:33 +08:00
bunnie
6deb750d6e Improve soc.svd output for eventmanager events 
Right now no data is created for which bit means what in
the soc.svd file. Attempt to extend event manager finalization
to use "fields" instead of bit positions, so that the SVD
file can auto-generate the events correctly.
 2020-11-15 16:33:14 +08:00
Florent Kermarrec
05f83ca978 tools/litex_term: minor cleanups (cosmetic). 2020-11-13 11:12:35 +01:00
Florent Kermarrec
5097b7ae5c boards: keep up to date with litex-boards, remove pcie_screamer target. 2020-11-12 18:16:56 +01:00
Florent Kermarrec
103c7e90a5 integration/soc/LiteXSoC: add initial add_pcie integration method. 2020-11-12 16:07:40 +01:00
Florent Kermarrec
7a4b26d2ba tools/litex_json2dts: fix missing {. 2020-11-12 14:45:46 +01:00
Florent Kermarrec
9c0f687922 build/generic_platform: use script filename as name when no Platform file. 2020-11-11 09:45:21 +01:00
Florent Kermarrec
275932f56c gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
Florent Kermarrec
2741fc2ba5 build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers. 
This will avoid programming errors to be silently ignored and will raise the following error:

OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.
 2020-11-10 10:22:57 +01:00
Florent Kermarrec
a5bdfe3f4c software/i2c: add i2c_scan command. 2020-11-10 09:47:28 +01:00
Florent Kermarrec
ce9f24748f soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high). 2020-11-10 09:46:43 +01:00
Florent Kermarrec
221ea4c31a tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4). 2020-11-09 16:36:04 +01:00
Florent Kermarrec
5aa70d975c tools/litex_server: revert CommUDP's max length to 1 (needs more testing). 2020-11-09 16:35:04 +01:00
Florent Kermarrec
1d04b1dd83 software/liblitesdcard: Operate the SDCard in 3.3V/High Speed. 
SDR50/Driver strength configuration is for 1.8V that is no longer supported
(for simplicity).
 2020-11-09 15:39:54 +01:00
Florent Kermarrec
b3a42d76ce cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class. 2020-11-09 13:31:11 +01:00
enjoy-digital
3673f38d63
Merge pull request #653 from gsomlo/gls-dt-cpufreq 
RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
 2020-11-09 12:40:15 +01:00
enjoy-digital
ecaf69fe78
Merge pull request #688 from rprinz08/master 
Fix check for wrong named attributes
 2020-11-09 11:22:08 +01:00
Florent Kermarrec
0627c01d89 soc/cores/spi_opi: move add_timing_constraints after __init__ to ease readability (first describe the logic then add the constraints). 2020-11-09 11:15:00 +01:00
enjoy-digital
5587ee5eea
Merge pull request #690 from betrusted-io/master 
Add arbitrary command (eg. write) capability to SPI DOPI
 2020-11-09 11:12:13 +01:00
enjoy-digital
80883ef37e
Merge pull request #689 from DurandA/patch-7 
libcompiler_rt: Remove duplicate mulsi3.o in Makefile
 2020-11-09 11:08:29 +01:00
Florent Kermarrec
50a47f551e soc/cores: create ram directory and move SPRAM/LRAM implementation to it. 
Will ease maintenance and future additions similarly to clock wrappers. Provide
retro-compatibily layer for Up5kSPRAM that we could remove after next release.
 2020-11-09 11:04:31 +01:00
Florent Kermarrec
ea8be6adcd targets/kcu105: add missing AsyncResetSynchronizer import. 2020-11-09 10:40:36 +01:00
Florent Kermarrec
14e196ab5d soc/cores/clock: create directory and split code in separate files to ease maintenance/adding new devices. 
clock.py was originally created/prototyped for 7-Series FPGAs, but has since been extended to almost all
FPGA devices supported by LiteX making it large enough to justify the split.

soc/cores/clock/__init__.py provides the retro-compatibily layer.
 2020-11-09 10:33:12 +01:00
bunnie
036ea48a4d update constraints to be in-line with litex methodology 2020-11-09 16:43:01 +08:00
davidcorrigan714
a6fd7b5d37 Lattice NX PLL Support 2020-11-08 20:34:10 -06:00
bunnie
b59711f89f Merge remote-tracking branch 'origin/master' 2020-11-08 14:35:41 +08:00
Arnaud Durand
2c36098f45
libcompiler_rt: Remove duplicate mulsi3.o in Makefile 2020-11-08 03:21:39 +01:00
rprinz08
09ecd9abc9 Make commUDP more reliable in case of bad Ethernet connection 2020-11-07 11:32:50 +01:00
rprinz08
1c039389f2 Fix check for wrong named attributes 2020-11-07 11:13:51 +01:00
bunnie
d892c6f8f5 minor bug fixes in spi writing; USB-based flashing is not working 2020-11-07 03:57:46 +08:00
Florent Kermarrec
9359aa0688 tools/litex_server: revert CommUDP's max length to 4 now that https://github.com/enjoy-digital/liteeth/issues/52 is fixed). 2020-11-06 19:50:25 +01:00
Florent Kermarrec
9fe3a42072 software/liblitedra/sdram: minor cleanup, use identical delay after each delay increment. 2020-11-06 16:11:25 +01:00
Florent Kermarrec
d1ef64f9fd tools/litex_server: revert CommUDP's max_length to 1. 
https://github.com/enjoy-digital/liteeth/issues/52 needs to be investigated before enabling _read_merger
on UDP.
 2020-11-06 13:01:56 +01:00
Florent Kermarrec
996be95725 tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki). 2020-11-06 12:49:43 +01:00
bunnie
fc59bcd833 add facility for burst writing and fix pp4b command bug 2020-11-06 04:43:23 +08:00
Florent Kermarrec
61c009a393 revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00
Florent Kermarrec
c088cd5d22 cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices. 2020-11-05 19:43:11 +01:00
Florent Kermarrec
3e47a6e48b get_data_mod: fix error message when module not found (pythondata modules are named only with "-" and not "_"). 2020-11-05 15:58:32 +01:00
Florent Kermarrec
65f19b5c4a integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST. 
sdram_bist command will then be available in the BIOS:

litex> sdram_bist
sdram_bist <burst_length> <random>
litex> sdram_bist 256 0
Starting SDRAM BIST with burst_length=256 and random=0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455            0            0
            473             455           25            0
            473             455           50            0
            473             455           75            0
            473             455          100            0
            473             455          125            0
            473             455          150            0
            473             455          175            0
            473             455          200            0
            473             455          225            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          250            0
            473             455          275            0
            473             455          300            0
            473             455          325            0
            473             455          350            0
            473             455          375            0
            473             455          400            0
            473             455          425            0
            473             455          450            0
            473             455          475            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          500            0
            473             455          525            0
            473             455          550            0
            473             455          575            0
            473             455          600            0
            473             455          625            0

litex>
 2020-11-05 13:41:37 +01:00
Florent Kermarrec
97b35a0771 software/liblitedram/bist: update generator/checker control to configure end CSR. 2020-11-05 13:39:48 +01:00
Florent Kermarrec
3dffdbf628 build/xilinx: add missing \n on error reporting. 2020-11-04 11:32:25 +01:00
Florent Kermarrec
897b2ea412 boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:15:04 +01:00
Florent Kermarrec
ffc554dede soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents. 2020-11-04 10:58:16 +01:00
Florent Kermarrec
2c504783ca bios/cmd/cmd_bios: add leds command to set leds value. 
Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.
 2020-11-04 10:22:14 +01:00
Florent Kermarrec
db836e8e5d build: add toolchain check before running build script and improve error reporting. 2020-11-04 09:42:18 +01:00
bunnie
6e806ce60c refactor SPI DOPI interface to support arbitrary commands, not jsut reads 
lays the groundwork for doing page programming and sector erasing
 2020-11-04 04:39:47 +08:00
Florent Kermarrec
f8cadc7b04 software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable). 2020-11-03 19:20:43 +01:00
enjoy-digital
b8d48385f6
Merge pull request #684 from sergachev/master 
cores/cpu/zynq7000: fix axi hp slave registration
 2020-11-03 14:53:10 +01:00
Florent Kermarrec
99b103998d software/liblitedram: expose sdram_bist_loop. 2020-11-03 13:03:45 +01:00
Florent Kermarrec
9d94bcdef7 boards/platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:59:12 +01:00
Florent Kermarrec
b63e2d3b94 boards/platforms: remove pcie_screamer (we'll add it to litex-boards). 2020-11-03 10:53:26 +01:00
Ilia Sergachev
cc652dda77 cores/cpu/zynq7000: fix axi hp slave registration 2020-11-03 00:55:16 +01:00
Florent Kermarrec
081d883421 targets/kc705: revert sys_clk_freq to 150MHz. 2020-11-02 19:52:28 +01:00
Florent Kermarrec
c1c095fdd4 targets/nexys_video: add SATA support. 2020-11-02 19:46:11 +01:00
Florent Kermarrec
cc95d89a6f boards/kc705: update sata integration. 2020-11-02 19:01:10 +01:00
Florent Kermarrec
d18157edde software/bios/cmd_litesata: add sata_init/sata_write commmands. 2020-10-30 15:38:45 +01:00
Florent Kermarrec
cb1badb173 software/liblitesata: add sata_write and update #ifdefs. 2020-10-30 15:38:17 +01:00
Florent Kermarrec
638d28d8d4 soc/sata: fix typo in Mem2Sector DMA. 2020-10-30 15:37:20 +01:00
Florent Kermarrec
060bbf1d59 soc/sata: add write support with LiteSATAMem2SectorDMA. 2020-10-30 12:20:12 +01:00
Florent Kermarrec
c4a6fe7d96 soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA). 2020-10-30 12:09:34 +01:00
Florent Kermarrec
7bcf8cb752 software/liblitedram: switch to uint32_t (as workaround for #322) and expose burst_length/random parameters to sdram_bist command. 2020-10-29 18:31:47 +01:00
Florent Kermarrec
07503d22ac soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata). 2020-10-29 15:06:02 +01:00
Florent Kermarrec
b9ceed0f74 integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check. 2020-10-29 10:50:10 +01:00
Florent Kermarrec
e7ad705359 integration/soc: add initial SATA integration with DMA read support. 2020-10-29 10:15:46 +01:00
bunnie
e8c39ec3d2 add generic command processing state machine 
facilitates page writes and sector erases
first commit, debugging now commencing
 2020-10-29 05:09:18 +08:00
Florent Kermarrec
9b123f7c9a software/liblitesata: implement sata_init with new CSR registers. 2020-10-28 19:55:19 +01:00
Florent Kermarrec
1fca7b9a91 software/liblitesata/sata_read: handle errors. 2020-10-28 18:59:36 +01:00
Florent Kermarrec
2bb46b305b software/liblitesata: fix warning, typo, add TODO. 2020-10-27 09:39:01 +01:00
Florent Kermarrec
c0ba03ef66 targets/kc705: add initial SATA support. 2020-10-26 15:14:40 +01:00
Florent Kermarrec
4127af36b5 soc/software: add initial minimal LiteSATA support (allow booting from SATA drive). 2020-10-26 15:13:56 +01:00
bunnie
37f2ebe675 add responder for type 0 cti, so that wb debug access works 2020-10-25 17:50:56 +08:00
Florent Kermarrec
c474272f53 soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why. 2020-10-23 14:33:24 +02:00
Florent Kermarrec
e94876753d soc/cores/icap: add back missing add_csr (was missing after adding add_reload method). 2020-10-23 08:00:43 +02:00
Florent Kermarrec
0dec446434 tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. 
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
 2020-10-22 17:45:45 +02:00
Florent Kermarrec
30b226f895 soc/intergration/export: additional name override fix. 2020-10-22 08:55:14 +02:00
enjoy-digital
abdc8bb26e
Merge pull request #681 from Disasm/fix-svd-soc-name 
Fix SoC name in SVD generator
 2020-10-22 08:53:32 +02:00
Florent Kermarrec
4eb634ba2d soc/interconnect/csr: fix CSRAccess values check. 2020-10-21 21:43:08 +02:00
enjoy-digital
e7b33a9ea8
Merge pull request #680 from daveshah1/dave/radiant-portname-fix 
radiant: Use {} string for bus port names
 2020-10-21 21:23:05 +02:00
enjoy-digital
7bbde6d05a
Merge pull request #679 from DurandA/patch-6 
Add integer limits to stdint.h
 2020-10-21 21:22:37 +02:00
Florent Kermarrec
c430587e91 soc/interconnect/stream/Shifter: add shift signal as optional parameter. 2020-10-21 15:52:53 +02:00
Vadim Kaushan
e4997295bd
Fix SoC name in SVD generator 
The name was overwritten with one of the CSR region names
 2020-10-21 16:40:35 +03:00
David Shah
66eb38cf84 radiant: Escape bus port names 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-21 14:05:33 +01:00
Florent Kermarrec
5a6b8f452d soc/interconnect/stream: add Shifter. 
Useful to shift stream data (ex for SerDes alignment).
 2020-10-21 12:47:55 +02:00