Sebastien Bourdeauducq
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b6763c28ea
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constant: equality
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2012-01-07 12:29:47 +01:00 |
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Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
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Sebastien Bourdeauducq
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f209bf6b33
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convtools -> tools
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2012-01-07 00:39:28 +01:00 |
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Sebastien Bourdeauducq
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0b195a244d
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flow: network
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2012-01-07 00:33:28 +01:00 |
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Sebastien Bourdeauducq
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3c1dada9cf
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record: compatibility check
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2012-01-06 23:00:23 +01:00 |
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Sebastien Bourdeauducq
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588f1a259e
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flow: plumbing
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2012-01-06 17:24:05 +01:00 |
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Sebastien Bourdeauducq
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8f1bf508ca
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actor: simplified automatic control
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2012-01-06 15:35:17 +01:00 |
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Sebastien Bourdeauducq
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a3bf877802
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ALA: use records for tokens
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2012-01-06 14:32:00 +01:00 |
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Sebastien Bourdeauducq
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038992e7d2
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corelogic: record
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2012-01-06 11:20:44 +01:00 |
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Sebastien Bourdeauducq
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d7a3bed44c
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Signal repr
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2012-01-06 11:20:33 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
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Sebastien Bourdeauducq
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edf90870c2
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flow: sum and division actors
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2011-12-23 00:35:53 +01:00 |
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Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
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Sebastien Bourdeauducq
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f0aac4b50f
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flow: actor class
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2011-12-22 19:37:16 +01:00 |
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Sebastien Bourdeauducq
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566295dea3
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csr: use optree
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2011-12-22 19:36:56 +01:00 |
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Sebastien Bourdeauducq
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ba40f58491
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corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
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Sebastien Bourdeauducq
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8a394f9159
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verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
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26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
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Sebastien Bourdeauducq
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7456195775
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Consistent names
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2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
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94c5fba067
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corelogic: fix signal exports
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2011-12-18 21:54:28 +01:00 |
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Sebastien Bourdeauducq
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4f4d809a4e
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fhdl: better matching of assignment
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2011-12-18 21:49:48 +01:00 |
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Sebastien Bourdeauducq
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107f03fd4b
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Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
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Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
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Sebastien Bourdeauducq
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41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
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Sebastien Bourdeauducq
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135a2eb868
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bank: support raw registers
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2011-12-18 00:28:04 +01:00 |
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Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
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Sebastien Bourdeauducq
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1a845d4553
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32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
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Sebastien Bourdeauducq
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6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
|
Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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929cc98070
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wishbone2csr: wait for WB deack
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2011-12-13 17:38:59 +01:00 |
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Sebastien Bourdeauducq
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22d03b4943
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timeline: only trigger in rest state
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2011-12-13 15:25:46 +01:00 |
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Sebastien Bourdeauducq
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c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
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Sebastien Bourdeauducq
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92f24b784d
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wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
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0ea7a9b2e6
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wishbone2csr: fix double-write bug
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2011-12-13 00:25:46 +01:00 |
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Sebastien Bourdeauducq
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923fc52e68
|
wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
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a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |
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Sebastien Bourdeauducq
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eee6980a36
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fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
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Sebastien Bourdeauducq
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dafef5d744
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fhdl: fix list references (thanks Lars)
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2011-12-11 20:17:29 +01:00 |
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Sebastien Bourdeauducq
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16a6029a1b
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bus: fix CSR interconnect data readback
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2011-12-11 20:17:12 +01:00 |
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Sebastien Bourdeauducq
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dad9120653
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bus: 14-bit CSR addresses
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2011-12-11 20:16:50 +01:00 |
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Sebastien Bourdeauducq
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7582b76406
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bank: fix csrgen address decoder
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2011-12-11 20:15:30 +01:00 |
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Sebastien Bourdeauducq
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05d91c7104
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bus: Wishbone to CSR bridge
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2011-12-11 15:04:34 +01:00 |
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Sebastien Bourdeauducq
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af74a89b8a
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corelogic: timeline module
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2011-12-11 01:11:13 +01:00 |
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Sebastien Bourdeauducq
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019ef16db4
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fhdl: remove broken fragment iadd
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2011-12-11 01:10:59 +01:00 |
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Sebastien Bourdeauducq
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b00581616e
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convtools: insert reset on variables
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2011-12-11 01:10:37 +01:00 |
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Sebastien Bourdeauducq
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d3127fd5d8
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autofragment: remove debug
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2011-12-10 20:48:23 +01:00 |