Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
7340 commits 42 branches 14 tags 31 MiB
Commit graph

3595 commits

Author SHA1 Message Date
Florent Kermarrec
8c3508e7f5 fhdl/verilog: Remove dummy_signal (no longer used). 2021-10-15 15:09:41 +02:00
Florent Kermarrec
f692f50d06 fhdl/verilog: Remove reg_initialization (always enabled in LiteX). 2021-10-15 15:01:41 +02:00
Florent Kermarrec
84e8fd0f9e fhdl/verilog: Add larger separators. 2021-10-15 14:55:46 +02:00
Florent Kermarrec
5a2399b037 fhdl/verilog: Remove display_run (not used in LiteX). 2021-10-15 14:43:42 +02:00
Florent Kermarrec
8aad25ae2b fhdl/verilog: Create _print_cat/_print_replicate, start cleaning up convert. 2021-10-15 14:25:33 +02:00
Florent Kermarrec
2c98ad94b5 fhdl/verilog: Create _print_operator/_print_slice, move code outside _print_expression and cleanup/simplify. 2021-10-15 13:54:06 +02:00
Florent Kermarrec
cdfb8d141a fhdl/verilog: Simplify _print_signal/_print_constant, add comments to _print_expression. 2021-10-15 11:51:39 +02:00
Florent Kermarrec
a18107f795 fhdl/verilog: Give more explict names to print functions. 2021-10-15 11:27:34 +02:00
Florent Kermarrec
86178ed2d9 fhdl/verilog: Update Reserved Keywords (from IEEE 1800-2017) and minor cleanup. 2021-10-15 11:06:31 +02:00
Michal Sieron
5b166b3aa4 Fix microwatt synthesis 
Microwatt uses now 29 bit wishbone addresses, so 3 additional bits for
compatibility are no longer needed.

Rest is minimal set of changes that was needed to make it build.
 2021-10-14 19:57:11 +02:00
Florent Kermarrec
adf30928d4 build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog. 2021-10-14 19:12:00 +02:00
Florent Kermarrec
2628140e8a soc_core: Also add "no_we" support to integrated_main_ram (and improve add_ram/add_rom calls). 2021-10-14 10:18:17 +02:00
Florent Kermarrec
8316fbf14b build/efinix/common: Fix EfinixAsyncResetSynchronizerImpl. 
SR_VALUE is set to 0 by default and needs to be set to 1.
 2021-10-13 16:31:47 +02:00
Florent Kermarrec
f0a3fcfefa build/efinix: Improve error message when Efinity toolchain is not found. 2021-10-13 14:41:44 +02:00
Florent Kermarrec
fd354c5759 gen/fhdl/memory: Fix dual clock memory pattern (previous pattern is no longer supported by Yosys), thanks @gregdavill. 
See https://github.com/enjoy-digital/litex/issues/1003.
 2021-10-13 11:33:43 +02:00
Florent Kermarrec
8fbd1b84a4 gen/fhdl: Use a local emit_verilog function for Memory. 
With the various FPGA now supported, being able to generate valid verilog patterns
that will be infered correctly is now complicated.

Use our local version of emit_verilog to be able to specialize more easily the generated
code.

This will also allow use to progressively remplace Migen's Memory.
 2021-10-13 10:58:49 +02:00
Florent Kermarrec
269b84eca4 build/efinix: Move tweaked Memory to build/efinix for now. 2021-10-13 09:51:47 +02:00
Florent Kermarrec
a99b4cac48 build/efinix: Minor initial cleanups. 2021-10-13 09:42:39 +02:00
enjoy-digital
eafa0fe83e
Merge pull request #1066 from fjullien/efinix 
Initial Efinix support.
 2021-10-13 09:17:32 +02:00
Florent Kermarrec
5e3e78f760 soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness. 2021-10-12 15:46:35 +02:00
enjoy-digital
f93b6b9f27
Merge pull request #1065 from shenki/microwatt-picolibc-family 
microwatt: Fix family property
 2021-10-12 09:08:57 +02:00
Florent Kermarrec
a489dadfbc cpu/CPUNone: Add ethmac to mem_map as temporary build workaround for --cpu-type=None --with-ethernet. 2021-10-12 09:02:48 +02:00
Joel Stanley
79ae6a99ab microwatt: Fix family property 
In commit 061b89beff ("cpu/picolibc: Add family property to CPUs and
directly use it for picolibc.") a family was added for meson cross
compilation, but this doesn't exist, leading to the following warning:

 WARNING: Unknown CPU family powerpc, please report this at https://github.com/mesonbuild/meson/issues/new

Instead use ppc64. While this seems wrong for a ppc64le machine, it
appears to be what meson expects.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-10-12 17:21:09 +10:30
Florent Kermarrec
96cfb44851 soc: Raise custom SoCError Exception and disable traceback/exception since already described. 2021-10-12 08:35:14 +02:00
Chris Osterwood
665665e1cc
Update icestorm.py with u4k device, since Yosys can target it 2021-10-08 15:20:39 -04:00
Florent Kermarrec
db20cb172d cores/video/VideoFrameBuffer: Add missing ClockDomainsRenamer on Converter (thanks @rdolbeau). 
Converter was not running in the right clock domain in ((dram_port.data_width > depth) and clock_faster_than_sys) case.
 2021-10-08 14:33:04 +02:00
Florent Kermarrec
f508b131ea cores/video: Change depth parameter to format (more explicit and we'll maybe want to support other video formats). 2021-10-08 14:28:04 +02:00
enjoy-digital
6d317d0882
Merge pull request #1053 from rdolbeau/fb_rgb565 
Add 16-bits, RGB565 FB support in simple-framebuffer
 2021-10-08 14:15:10 +02:00
Gabriel Somlo
18bd8f3770 cpu/rocket: add dual-core (smp) variants 
- 2-core "linux" (fpu-less) variants with double, quad mem. bus width
 2021-10-06 08:48:27 -04:00
Florent Kermarrec
f03a15820b tools/litex_sim: Remove useless pre_run_callback toolchain attribute. 2021-10-06 09:16:08 +02:00
enjoy-digital
04885a5d77
Merge pull request #1057 from antmicro/rocket-asm-alignment 
cpu/rocket: naturally align data defined in crt0.S
 2021-10-04 17:57:43 +02:00
Florent Kermarrec
99f3498f2d cores/icap/ICAP: Add Register read capability. 
Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
 2021-10-04 17:22:57 +02:00
Jakub Piecuch
771897fa37 cpu/rocket: naturally align data defined in crt0.S 
The startup code accesses this data using sd/ld instructions, which
require that the address being accessed is 8-byte aligned.
The .dword asm directive does NOT imply any alignment, so we need
to force it using the .align directive.
 2021-10-04 15:22:13 +02:00
Florent Kermarrec
3504904c09 cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend). 2021-10-04 15:06:03 +02:00
Florent Kermarrec
9416e30249 test/test_icap: Add IPROG sequence check. 2021-10-04 14:41:38 +02:00
Florent Kermarrec
cb2f2d7021 cores/icap/ICAP: Rewrite using constants and cleanup. 2021-10-04 14:25:40 +02:00
Florent Kermarrec
1f2b143c66 cores/icap: Add Configuration Registers and Commands definition. 2021-10-04 13:35:36 +02:00
Florent Kermarrec
6b3b243bb3 cores/icap: Fix/Update comment. 2021-10-04 11:37:40 +02:00
Florent Kermarrec
cb6861e1c8 build: Add initial/minimal QuickLogic build support. 2021-10-01 11:42:56 +02:00
Gabriel Somlo
d92f10dfb0 64-bit follow-up for picolibc warning fixes 
Providing "uint32_t" to printf's "%ld" results in warnings on 64-bit
builds: use "unsigned long" instead.
 2021-09-30 20:26:40 -04:00
Romain Dolbeau
bf004d48e9 Add 16-bits, RGB565 FB support in simple-framebuffer 2021-09-30 19:40:03 +02:00
Florent Kermarrec
77283d3d8d software: Fix picolibc compilation warnings. 2021-09-30 19:24:58 +02:00
Florent Kermarrec
841732f38f software/liblitesata: Fix compilation with picolibc. 2021-09-30 18:56:01 +02:00
enjoy-digital
7b7fd25d5d
Merge pull request #1054 from niw/fix_disk_read_arg_name 
FIX: arg name is changed.
 2021-09-30 17:44:33 +02:00
Yoshimasa Niwa
abcf5f1d7b FIX: arg name is changed. 2021-09-30 02:56:19 -07:00
Florent Kermarrec
47e4a1b437 tools/litex_term: Avoid staying in safe mode on next upload when previous calibration failed. 2021-09-30 10:11:48 +02:00
Florent Kermarrec
5661480409 tools/litex_term: Add automatic inter-frame delay calibration and --safe mode. 
By default, litex_term will now automatically try to find the best inter-frame delay/payload length
parameters to optimize upload speed. The --safe mode can also be used to disable outstanding frames
(and then wait ack for each frame), it will be slow on regular UARTs (that have high round-trip
latencis) but should always work.
 2021-09-29 18:41:06 +02:00
Florent Kermarrec
80cb53fb04 software/bios/boot: Allow frame reception to time out during serial boot and do some cleanup/add comments. 
Allowing the serial boot to time out during frame reception allows doing test on the Host side to
calibrate the minimum inter-frame delay and maximum payload length.

In the future, we should probably compute the CRC directly during frame reception and do the mempcpy
of frame N during the reception of frame N+1 to avoid these inter-frame constraints.
 2021-09-29 18:33:59 +02:00
Franck Jullien
93c470aecb Efinix: add a local video.py with VideoLVDSPHY for testing 2021-09-28 18:08:03 +02:00
Franck Jullien
a08c5201ad Efinix: improve ifacewriter + misc 2021-09-28 18:06:57 +02:00
Franck Jullien
45961f733b Efinix: instance of dbparser class now in platform 2021-09-28 18:06:23 +02:00
Franck Jullien
b2e09832e5 Efinix: dbparser, add get_gpio_instance_from_pin 2021-09-28 18:04:49 +02:00
Franck Jullien
32f4d246f4 Efinic ConstraintManager improve delete method 2021-09-28 18:04:27 +02:00
Florent Kermarrec
5a35aa9df6 software/libliteeth: Fix missing prototype warnings. 2021-09-28 17:46:23 +02:00
Florent Kermarrec
9a931324c2 get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed. 2021-09-28 16:27:13 +02:00
Karol Gugala
9f1108c2fc libc: refactor picolibc build deps 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:30 +02:00
Karol Gugala
b9c4d7ba51 libc: add _impure_ptr definition 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:08 +02:00
Karol Gugala
22f50ec7ff libc: add errno include 
This solves missing `__errno` symbol linker errors

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:16:34 +02:00
Florent Kermarrec
a588c3b830 software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket). 2021-09-28 14:51:02 +02:00
Florent Kermarrec
061b89beff cpu/picolibc: Add family property to CPUs and directly use it for picolibc. 2021-09-28 14:20:13 +02:00
Florent Kermarrec
b451f102c6 software/libc/stdio: Simplify/Cleanup. 2021-09-28 14:04:24 +02:00
Florent Kermarrec
12c93ea895 litex_sim: Generate gtkw_savefile only with --trace. 2021-09-28 13:32:12 +02:00
Florent Kermarrec
782744bae3 tools/litex_sim/generate_gtkw_savefile: Check main_ram presence. 2021-09-28 10:02:17 +02:00
Florent Kermarrec
de738e153d tools/litex_sim: Avoid double build iteration with pre_run_callback function. 2021-09-28 09:58:43 +02:00
Florent Kermarrec
c98c777bed integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups. 2021-09-28 08:57:49 +02:00
Karol Gugala
d101ef7ed0 software: libc: fix Makefile dependecies 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-27 23:05:54 +02:00
Florent Kermarrec
01a906add7 software/liblitesdcard: Fix compilation with picolibc. 2021-09-27 18:56:18 +02:00
Florent Kermarrec
727d898a6c software/libliteeth: Update/Fix compilation with picolibc. 2021-09-27 18:54:28 +02:00
enjoy-digital
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii 2021-09-27 17:47:26 +02:00
Florent Kermarrec
9ab82cacda soc/add_ethernet/etherbone: Fix conflicts/Update. 2021-09-27 17:43:39 +02:00
enjoy-digital
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter 
cpu/rocket/core: Remove ResetInserter on adapters.
 2021-09-27 16:34:46 +02:00
Florent Kermarrec
3d32ac3d2e software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility. 
We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).

In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
 2021-09-27 16:15:13 +02:00
Florent Kermarrec
ae1d43b965 software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
enjoy-digital
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement 
Replace libbase with picolibc
 2021-09-27 16:05:24 +02:00
Florent Kermarrec
944732aa19 soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone. 2021-09-27 15:46:19 +02:00
Franck Jullien
06ff638f7a efinix: rgmii: fix, it's in a working state 2021-09-27 10:11:58 +02:00
Franck Jullien
1ea0797c82 efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ 2021-09-27 10:11:00 +02:00
Florent Kermarrec
ce0551b44a cpu/rocket/core: Remove ResetInserter on adapters. 
Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
 2021-09-27 09:05:46 +02:00
Franck Jullien
179a8018b3 efinix: RGMII phy should be operational (no tested) 
PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:

ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.

Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
 2021-09-23 17:21:17 +02:00
Gabriel Somlo
07e47d9357 cpu/rocket: add quad-core (smp) variants 
- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
 2021-09-22 16:59:04 -04:00
Gabriel Somlo
901b19828c cpu/rocket: include core count as per-variant parameter 
Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
 2021-09-22 16:58:11 -04:00
Gabriel Somlo
e6aaa40d2d cpu/rocket: bios support for SMP 2021-09-22 13:51:18 -04:00
Gabriel Somlo
2bc8124114 cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic) 2021-09-22 13:51:18 -04:00
enjoy-digital
1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix 
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
 2021-09-22 19:35:47 +02:00
Florent Kermarrec
60c6077c32 remote/comm_udp: Add padding bytes to Etherbone probe. 
Now required with LiteEth dropping exceeding payload.
 2021-09-22 16:52:08 +02:00
Gabriel Somlo
23b2ac2013 cpu/vexriscv_smp/crt0.S: only boot core should run data_init 
Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
 2021-09-22 09:55:20 -04:00
Franck Jullien
109dbd1d62 efinity: small fixes 
- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
 2021-09-22 09:53:27 +02:00
Franck Jullien
b24475b07d Add an hacked no we memory for Efinix 
Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.

This class needs to be rewrite !
 2021-09-22 09:47:51 +02:00
Florent Kermarrec
027f7aa645 tools/litex_json2dts_linux: Fix typo. 2021-09-21 14:32:20 +02:00
Franck Jullien
bd71dc663f efinix: more DDR work, still WIP 2021-09-21 14:23:36 +02:00
Franck Jullien
b765bdf34e efinix: pll: allow output name to be changed 2021-09-21 14:23:00 +02:00
Franck Jullien
7a5f5a3682 efinix: remove redundant param in _build_xml 2021-09-21 14:22:17 +02:00
Florent Kermarrec
84f1afd6d4 tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs. 
Were not useful as pointed by @shenki and @stffrdhrn.
 2021-09-21 13:37:25 +02:00
enjoy-digital
b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard 
Json2dts sdcard booting
 2021-09-21 13:13:07 +02:00
Franck Jullien
24a920f2d1 efinix: add preliminary DDR support (WIP) 2021-09-21 10:58:54 +02:00
Andwer E Wilson
9f75c73d6b build/xilinx/common: Fix Ultrascale SDROutput/Input. 2021-09-21 10:30:36 +02:00
enjoy-digital
233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok 
Remove rsp_payload_response_ok from Vex/CFU hookup code.
 2021-09-21 09:43:15 +02:00
Florent Kermarrec
08779202f4 build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap). 2021-09-21 08:18:06 +02:00
Tim Callahan
1be449d72b Remove rsp_payload_response_ok from Vex/CFU hookup code. 
The port has already been removed from VexRiscv (issue #1036).

Signed-off-by: Tim Callahan <tcal@google.com>
 2021-09-20 15:02:51 -07:00
Florent Kermarrec
1e24fd87d1 cores/gpio: Simplify #1035. 2021-09-20 17:34:46 +02:00