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3595 commits

Author SHA1 Message Date
Franck Jullien
45961f733b Efinix: instance of dbparser class now in platform 2021-09-28 18:06:23 +02:00
Franck Jullien
b2e09832e5 Efinix: dbparser, add get_gpio_instance_from_pin 2021-09-28 18:04:49 +02:00
Franck Jullien
32f4d246f4 Efinic ConstraintManager improve delete method 2021-09-28 18:04:27 +02:00
Florent Kermarrec
5a35aa9df6 software/libliteeth: Fix missing prototype warnings. 2021-09-28 17:46:23 +02:00
Florent Kermarrec
9a931324c2 get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed. 2021-09-28 16:27:13 +02:00
Karol Gugala
9f1108c2fc libc: refactor picolibc build deps 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:30 +02:00
Karol Gugala
b9c4d7ba51 libc: add _impure_ptr definition 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:08 +02:00
Karol Gugala
22f50ec7ff libc: add errno include 
This solves missing `__errno` symbol linker errors

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:16:34 +02:00
Florent Kermarrec
a588c3b830 software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket). 2021-09-28 14:51:02 +02:00
Florent Kermarrec
061b89beff cpu/picolibc: Add family property to CPUs and directly use it for picolibc. 2021-09-28 14:20:13 +02:00
Florent Kermarrec
b451f102c6 software/libc/stdio: Simplify/Cleanup. 2021-09-28 14:04:24 +02:00
Florent Kermarrec
12c93ea895 litex_sim: Generate gtkw_savefile only with --trace. 2021-09-28 13:32:12 +02:00
Florent Kermarrec
782744bae3 tools/litex_sim/generate_gtkw_savefile: Check main_ram presence. 2021-09-28 10:02:17 +02:00
Florent Kermarrec
de738e153d tools/litex_sim: Avoid double build iteration with pre_run_callback function. 2021-09-28 09:58:43 +02:00
Florent Kermarrec
c98c777bed integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups. 2021-09-28 08:57:49 +02:00
Karol Gugala
d101ef7ed0 software: libc: fix Makefile dependecies 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-27 23:05:54 +02:00
Florent Kermarrec
01a906add7 software/liblitesdcard: Fix compilation with picolibc. 2021-09-27 18:56:18 +02:00
Florent Kermarrec
727d898a6c software/libliteeth: Update/Fix compilation with picolibc. 2021-09-27 18:54:28 +02:00
enjoy-digital
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii 2021-09-27 17:47:26 +02:00
Florent Kermarrec
9ab82cacda soc/add_ethernet/etherbone: Fix conflicts/Update. 2021-09-27 17:43:39 +02:00
enjoy-digital
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter 
cpu/rocket/core: Remove ResetInserter on adapters.
 2021-09-27 16:34:46 +02:00
Florent Kermarrec
3d32ac3d2e software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility. 
We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).

In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
 2021-09-27 16:15:13 +02:00
Florent Kermarrec
ae1d43b965 software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
enjoy-digital
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement 
Replace libbase with picolibc
 2021-09-27 16:05:24 +02:00
Florent Kermarrec
944732aa19 soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone. 2021-09-27 15:46:19 +02:00
Franck Jullien
06ff638f7a efinix: rgmii: fix, it's in a working state 2021-09-27 10:11:58 +02:00
Franck Jullien
1ea0797c82 efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ 2021-09-27 10:11:00 +02:00
Florent Kermarrec
ce0551b44a cpu/rocket/core: Remove ResetInserter on adapters. 
Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
 2021-09-27 09:05:46 +02:00
Franck Jullien
179a8018b3 efinix: RGMII phy should be operational (no tested) 
PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:

ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.

Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
 2021-09-23 17:21:17 +02:00
Gabriel Somlo
07e47d9357 cpu/rocket: add quad-core (smp) variants 
- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
 2021-09-22 16:59:04 -04:00
Gabriel Somlo
901b19828c cpu/rocket: include core count as per-variant parameter 
Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
 2021-09-22 16:58:11 -04:00
Gabriel Somlo
e6aaa40d2d cpu/rocket: bios support for SMP 2021-09-22 13:51:18 -04:00
Gabriel Somlo
2bc8124114 cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic) 2021-09-22 13:51:18 -04:00
enjoy-digital
1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix 
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
 2021-09-22 19:35:47 +02:00
Florent Kermarrec
60c6077c32 remote/comm_udp: Add padding bytes to Etherbone probe. 
Now required with LiteEth dropping exceeding payload.
 2021-09-22 16:52:08 +02:00
Gabriel Somlo
23b2ac2013 cpu/vexriscv_smp/crt0.S: only boot core should run data_init 
Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
 2021-09-22 09:55:20 -04:00
Franck Jullien
109dbd1d62 efinity: small fixes 
- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
 2021-09-22 09:53:27 +02:00
Franck Jullien
b24475b07d Add an hacked no we memory for Efinix 
Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.

This class needs to be rewrite !
 2021-09-22 09:47:51 +02:00
Florent Kermarrec
027f7aa645 tools/litex_json2dts_linux: Fix typo. 2021-09-21 14:32:20 +02:00
Franck Jullien
bd71dc663f efinix: more DDR work, still WIP 2021-09-21 14:23:36 +02:00
Franck Jullien
b765bdf34e efinix: pll: allow output name to be changed 2021-09-21 14:23:00 +02:00
Franck Jullien
7a5f5a3682 efinix: remove redundant param in _build_xml 2021-09-21 14:22:17 +02:00
Florent Kermarrec
84f1afd6d4 tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs. 
Were not useful as pointed by @shenki and @stffrdhrn.
 2021-09-21 13:37:25 +02:00
enjoy-digital
b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard 
Json2dts sdcard booting
 2021-09-21 13:13:07 +02:00
Franck Jullien
24a920f2d1 efinix: add preliminary DDR support (WIP) 2021-09-21 10:58:54 +02:00
Andwer E Wilson
9f75c73d6b build/xilinx/common: Fix Ultrascale SDROutput/Input. 2021-09-21 10:30:36 +02:00
enjoy-digital
233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok 
Remove rsp_payload_response_ok from Vex/CFU hookup code.
 2021-09-21 09:43:15 +02:00
Florent Kermarrec
08779202f4 build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap). 2021-09-21 08:18:06 +02:00
Tim Callahan
1be449d72b Remove rsp_payload_response_ok from Vex/CFU hookup code. 
The port has already been removed from VexRiscv (issue #1036).

Signed-off-by: Tim Callahan <tcal@google.com>
 2021-09-20 15:02:51 -07:00
Florent Kermarrec
1e24fd87d1 cores/gpio: Simplify #1035. 2021-09-20 17:34:46 +02:00
enjoy-digital
6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio 
litex_sim: optionally add GPIOTristate core
 2021-09-20 17:21:29 +02:00
enjoy-digital
0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate 
build/lattice: add DDRTristate for Crosslink-NX
 2021-09-20 14:14:40 +02:00
Florent Kermarrec
49d8000d49 gowin/common: Add Differential Input/Output support. 2021-09-20 14:14:06 +02:00
Franck Jullien
b9e99f576c efinix: use proper xml to create project file 2021-09-20 13:35:45 +02:00
Florent Kermarrec
9c373242af gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern. 2021-09-20 11:47:32 +02:00
Maciej Kurc
6c0a758468 Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:02:01 +02:00
Franck Jullien
efebefecea efinix: add PLL reset and locked pins 2021-09-20 10:42:27 +02:00
Franck Jullien
a026dd8946 efinix: add AsyncResetSynchronizer 2021-09-20 10:41:59 +02:00
Franck Jullien
08be77caaf efinix: ifacewriter, enable design generation 2021-09-20 10:41:00 +02:00
Florent Kermarrec
5519d908e8 cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k). 2021-09-20 09:29:05 +02:00
Franck Jullien
106b1f29a7 efinix: fix programmer load_bitstream 2021-09-20 08:42:27 +02:00
Florent Kermarrec
4fe085cc1c cores/clock: Add initial GW1NSR's PLL support. 2021-09-20 08:39:25 +02:00
Florent Kermarrec
76c782c546 inetgration/builder: Check for full software re-build only when a CPU is used. 2021-09-20 08:31:22 +02:00
Franck Jullien
9b6ae2ff03 efinix: support PLL, add dbparser and ifacewriter 2021-09-20 07:56:53 +02:00
Franck Jullien
0278d3eee8 generic_platform: add a method to delete a constraint 2021-09-20 07:51:26 +02:00
Florent Kermarrec
46cd9c5a5c tools: Minor #1030 cleanups. 2021-09-17 14:37:48 +02:00
Florent Kermarrec
8ccb1a91c9 build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available. 2021-09-17 14:37:14 +02:00
enjoy-digital
24f0432253
Merge pull request #1030 from teknoman117/fix-lxserver-pcie-crossover 
Fixes to allow crossover uart over PCIe with lxterm and litex_server
 2021-09-17 14:28:25 +02:00
enjoy-digital
a7c9e4ed42
Merge pull request #1033 from caverar/patch-1 
Linker fix for initialized global variables
 2021-09-17 14:23:44 +02:00
Franck Jullien
000aabf85b Initial Efinix Trion support 2021-09-17 09:29:53 +02:00
Florent Kermarrec
7f8e2e39f3 cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes. 2021-09-16 18:56:05 +02:00
Pawel Sagan
e8e14d8ca5 build/lattice: add DDRTristate for Crosslink-NX 2021-09-16 14:23:02 +02:00
Michal Sieron
f2a05e92fa Add missing include to or1k/exception.c 2021-09-16 10:44:09 +02:00
Michal Sieron
3d4a64e112 Update stdio code in libc 
Picolibc now requires to create stdin, stdout and stderr files
ourselves instead of __iob array. Thus changes and renaming
of iob.c to stdio.c

f320a0aa17
added option to select default printf format, so using
picolibc.specs or defining PRINTF_LEVEL is no longer needed.
 2021-09-16 10:44:07 +02:00
Michal Sieron
ef7b287248 Disable thread local storage (TLS) in picolibc 
It was causing some compilation issues with lm32.
As global errno was enabled anyway, it was easier 
to disable TLS whatsoever.
 2021-09-16 10:43:44 +02:00
Michal Sieron
c84105f399 Disable LTO for picolibc and use picolibc.specs 
Use picolibc.specs to specify integer only printf/scanf.

To do that, we need to pass specs file with options to
the linker. With LTO enabled, name mapping was failing,
so LTO is now disabled for picolibc compilation only.

This also means, that exchange.c and arc4random.c no
longer need to be recompiled and added back.
 2021-09-16 10:43:41 +02:00
Michal Sieron
49c4ae9ec9 Add ppc64le-linux[-musl] to microwatt gcc triples 2021-09-16 10:42:54 +02:00
Michal Sieron
72e7eac0ef Fix demo compilation 2021-09-16 10:42:54 +02:00
Michal Sieron
befd9c0e4c Add comment documenting libc/missing.c 2021-09-16 10:42:54 +02:00
Michal Sieron
63094205d7 Add comment documenting libc/iob.c 2021-09-16 10:42:54 +02:00
Michal Sieron
c96c7f5c45 Fix machine specific directory copying 2021-09-16 10:42:54 +02:00
Michal Sieron
d3c23fb048 Remove libmisc 2021-09-16 10:42:54 +02:00
Michal Sieron
7fcc094b63 Don't filter out INCLUDE flags 2021-09-16 10:42:54 +02:00
Michal Sieron
cf59481567 Move machine specific code to their directories 2021-09-16 10:42:54 +02:00
Michal Sieron
66c54de785 Move sim_debug to the BIOS directory 2021-09-16 10:42:54 +02:00
Michal Sieron
b960ba0a67 Move stuff out of libbase 
Removed libbase completely and moved remaining files into
libutils, libcomm and libmisc.

Libcomm is place for code used for communicating with other
devices, which doesn't yet live in its own liblite*.

Libutils is code used in multiple places, like crc calculation,
progress bar, memtests.

Libmisc is everything else like sim_debug, which is code for
litex_sim or exception.c for or1k.
 2021-09-16 10:42:54 +02:00
Michal Sieron
91ce95fb49 Remove obsolete _include/dyld_ 
As per b5048f6cf1
it was necessary by libunwind, which we aren't building.
 2021-09-16 10:42:54 +02:00
Michal Sieron
6dc4908d12 Remove obsolete _include/basec++_ 
As per 7a9975ab5a
it was necessary to build libunwind, which we aren't building.
 2021-09-16 10:42:54 +02:00
Michal Sieron
b95acb8182 Remove obsolete _include/fdlibm_ 2021-09-16 10:42:54 +02:00
Michal Sieron
1a1a81bfa0 Move _exit function up, so gcc doesn't complain 2021-09-16 10:42:54 +02:00
Michal Sieron
9f169d5520 Enable long long support in IO operations 2021-09-16 10:42:54 +02:00
Michal Sieron
351a0713af Remove unused base/uart.h include 2021-09-16 10:42:54 +02:00
Michal Sieron
26c5a8a926 Move libbase/id.c to bios/cmd/cmd_bios.c 2021-09-16 10:42:54 +02:00
Michal Sieron
6bff5f1734 Replace inet.h with arpa/inet.h 2021-09-16 10:42:54 +02:00
Michal Sieron
082d1231f6 Remove obsolete time.c 2021-09-16 10:42:54 +02:00
Michal Sieron
823edfad22 Remove obsolete div64.c 2021-09-16 10:42:54 +02:00
Michal Sieron
8e4e3b5438 Enable LTO 
Use gcc-ar and gcc-nm, because they have LTO plugins

Turn off LTO for libcompiler_rt, exchange.c and arc4random.c
from newlib.

Also add getentropy, dummy function, because for some reason
libbase/console.c wants it.
 2021-09-16 10:42:29 +02:00
Michal Sieron
53135eb7bc Add missing definitions if target is microwatt 
Picolibc compilation for powerpc was missing some defines.
This adds them to gcc parameters
 2021-09-16 10:41:05 +02:00
Michal Sieron
ba1d20f2ad Add missing functions to make lm32 and or1k link 
I added missing.c with functions that were preventing
LiteX from successfull linking on lm32 and or1k.
 2021-09-16 10:41:05 +02:00
Michal Sieron
4e50c0ba00 Enable global errno 
Brings mor1kx compilation to the same error as lm32
 2021-09-16 10:41:05 +02:00
Michal Sieron
ab881c561f Implement initial support for lm32 and or1k 
Picolibc doesn't maintain meson.build or cross*.txt files
for lm32 and or1k CPUs.

This commit adds meson.build files for both of them.
Also libc/Makefile got modifed to determine CPU family
from $(CPU) value and generate cross.txt file.
Now picolibc gets compiled with LiteX flags too.

It doesn't compile on neither of them yet,
but at least riscv still works.
 2021-09-16 10:41:05 +02:00
Michal Sieron
ca4e17d886 Disable float support in tinystdio 
Float support was originally disabled in libbase
 2021-09-16 10:41:05 +02:00
Michal Sieron
b34adcf929 Remove libbase-nofloat.a variant 
As vsnprintf is no longer compiled it was
identical to libbase.a.

Picolibc defines levels of printf and scanf
https://github.com/picolibc/picolibc/blob/main/doc/printf.md#printf-and-scanf-levels-in-picolibc
so those should probably be used.
 2021-09-16 10:41:05 +02:00
Michal Sieron
c4ba313b86 Remove unnecessary header and source files 2021-09-16 10:41:05 +02:00
Michal Sieron
a6094fd418 Move libbase/console.c logic to libc/iob.c 2021-09-16 10:41:05 +02:00
Michal Sieron
768961ec59 Use getchar/putchar instead of readchar/base_putchar 2021-09-16 10:41:05 +02:00
Michal Sieron
ead3f8b2e0 Compile iob.c with $(compile) 2021-09-16 10:41:05 +02:00
Michal Sieron
8a38a79967 Remove unnecessary headers 2021-09-16 10:41:05 +02:00
Michal Sieron
10927691c5 Remove base and add picolibc to include search paths 2021-09-16 10:41:05 +02:00
Michal Sieron
19966edb61 Replace putsnonl(s) with fputs(s, stdout) 
It won't compile, because stdout is undefined, but
including headers from picolibc should fix that
 2021-09-16 10:41:05 +02:00
Michal Sieron
acf3a4570b Create __iob for picolibc 
Picolibc requires __iob array for its IO functions

This commit creates such array with dummy functions
using putchar/readchar from console.c

To prevent name conflicts printf and others were
removed from console.c

Also putchar had to be renamed to base_putchar
 2021-09-16 10:41:05 +02:00
Michal Sieron
db390537a9 Compile entire picolibc 
It does not compile yet, will need __iob array to be defined
Also there are multiple definitions of some functions
 2021-09-16 10:41:05 +02:00
Michal Sieron
6de59bdbc0 Incorporate picolibc into the build process 
Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command

Tested with digilent_arty.py
 2021-09-16 10:41:05 +02:00
Michał Sieroń
e25ca4082b Apply patch removing need for most of libbase 2021-09-16 10:41:05 +02:00
enjoy-digital
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll 
Fix premature selection of full PLL config with no feedback
 2021-09-15 08:52:59 +02:00
George Hilliard
91ec6e0da8 clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond 
Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs.  Emit the same attributes that Diamond's PLL tool does.
 2021-09-15 00:07:43 -05:00
George Hilliard
6733a3e3e6 clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search 2021-09-15 00:07:43 -05:00
Florent Kermarrec
88d302d4db soc/alloc_region: Ensure allocated Region is aligned on size. 2021-09-14 18:08:07 +02:00
Florent Kermarrec
694878a35a integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints. 
Some boards require specific constraints, so disable them in this case and put constraints in the target file.
 2021-09-13 19:32:50 +02:00
Leon Schuermann
8670ac4902 litex_sim: add optional GPIOTristate core 
Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-13 12:33:41 +02:00
Florent Kermarrec
cb7b0f44cf tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
Leon Schuermann
af8459301c litex/soc/cores/gpio: support external tristate buffer 
Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-13 11:17:54 +02:00
Camilo Andres Vera Ruiz
a235eaf0cd
Linker fix for initialized global variables 
I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
 2021-09-13 00:44:30 -05:00
Stafford Horne
ea06948c62 json2dts_linux: Add configuration for root device 
This allows setting a root device other than ram0, this is useful
when using a rootfs from the SD card.  Doing this makes boot time
faster and saves on memory footprint used by an in ram initrd.
 2021-09-12 14:44:22 +09:00
Stafford Horne
ec2f2a6af5 json2dts_linux: Use liteuart earlycon 
Now that liteuart earlycon is upstream we can use it.  This means
all litex soc's should be able to get an earlycon now.  Tested on
mor1kx.
 2021-09-12 14:42:52 +09:00
Stafford Horne
378d129c5f json2dts_linux: Allow disabling of initrd 2021-09-12 14:42:46 +09:00
Leon Schuermann
6cacdcd926 {Dep,p}acketizer: handle transactions of a single bus word 2021-09-09 16:36:21 +02:00
Leon Schuermann
2e8586a090 {Dep,P}acketizer: properly handle last_be wraparound 
While the Depacketizer did correctly calculate a new last_be value for
the data with the header removed, it may happen that the last_be
overflows and thus relates to the current, non-delayed sink value. The
same goes for the Packetizer, just inversed. This introduces logic in
form of a simple FSM to handle these cases and properly output last_be
on the last valid bus word.

Co-authored-by: David Sawatzke <d-git@sawatzke.dev>
Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-09 16:08:12 +02:00
Nathaniel R. Lewis
ab3d7e86f2 litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe 2021-09-08 18:06:12 -07:00
Florent Kermarrec
e0e9311ceb interconnect/wishbone: Specify Wishbone version (#999). 2021-09-08 17:33:01 +02:00
Florent Kermarrec
6c2bc02323 build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names. 
This makes it similar to add_platform_command and add more flexibility to constraint the design.
 2021-09-08 16:14:58 +02:00
Florent Kermarrec
0222697f21 liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size. 
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.

This will be less accurate but will still provide representative results which
is the aim of this test.
 2021-09-08 09:10:21 +02:00
Florent Kermarrec
10c4523c32 soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY. 2021-09-07 15:09:05 +02:00
Florent Kermarrec
575af6fc60 litespi/integration: Review/Cleanup #1024. 
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
 2021-09-07 14:36:13 +02:00
enjoy-digital
aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor 
litex: adding litespi to simulation, making litespi compatible with new implementation
 2021-09-07 13:17:40 +02:00
wuhanstudio
5d9880888c fix: missing colon syntax error 2021-09-07 11:21:41 +01:00
Florent Kermarrec
a6f9ac58bb build/sim/common: Review/Cleanup #1021 for consistency with other backends. 2021-09-07 09:44:43 +02:00
enjoy-digital
2b700057b7
Merge pull request #1021 from antmicro/ddr_sim 
litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
 2021-09-07 09:38:14 +02:00
Florent Kermarrec
7c50f52a57 tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets. 
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
 2021-09-07 09:27:51 +02:00
enjoy-digital
1598b5958d
Merge pull request #1017 from asadaleem-rs/master 
customize main ram size from command line argument
 2021-09-07 09:15:55 +02:00
Florent Kermarrec
e257d91d46 cpu/vexriscv: Review/Cleanup #1022. 
Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
 2021-09-07 09:04:47 +02:00
enjoy-digital
6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache 
Restructure config flags for dcache/icache presence in Vex.
 2021-09-07 08:46:03 +02:00
Tim Ansell
bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes 
Binutils fixes
 2021-09-06 17:16:56 -07:00
Pawel Sagan
ad0fcc22e6 litex: adding legacy mode for litespi 
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
 2021-09-03 09:42:41 +02:00
Florent Kermarrec
fa5fd765a4 interconnect/packet: Add dummy to omit list, fixes #1018. 2021-09-02 18:02:16 +02:00
Florent Kermarrec
7bd06d178f cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV). 2021-09-02 15:12:16 +02:00
Pawel Sagan
3cf6126663 litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate 2021-09-02 14:33:16 +02:00
Piotr Binkowski
25e0153dd5 litex_sim: use flash model in simulation 2021-09-02 14:33:16 +02:00
Pawel Sagan
837de615e6 liblitespi: adjusting code to oddr/iddr litespi implementation 
Changing litespi registers configuration to be compatible
with a new implementation.
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
 2021-09-02 14:33:11 +02:00
Pawel Sagan
0c91bb7b96 litex_sim: adding spi-flash option to simulation 
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
 2021-09-02 14:22:34 +02:00