Commit graph

3595 commits

Author SHA1 Message Date
Michal Sieron
ab881c561f Implement initial support for lm32 and or1k
Picolibc doesn't maintain meson.build or cross*.txt files
for lm32 and or1k CPUs.

This commit adds meson.build files for both of them.
Also libc/Makefile got modifed to determine CPU family
from $(CPU) value and generate cross.txt file.
Now picolibc gets compiled with LiteX flags too.

It doesn't compile on neither of them yet,
but at least riscv still works.
2021-09-16 10:41:05 +02:00
Michal Sieron
ca4e17d886 Disable float support in tinystdio
Float support was originally disabled in libbase
2021-09-16 10:41:05 +02:00
Michal Sieron
b34adcf929 Remove libbase-nofloat.a variant
As vsnprintf is no longer compiled it was
identical to libbase.a.

Picolibc defines levels of printf and scanf
https://github.com/picolibc/picolibc/blob/main/doc/printf.md#printf-and-scanf-levels-in-picolibc
so those should probably be used.
2021-09-16 10:41:05 +02:00
Michal Sieron
c4ba313b86 Remove unnecessary header and source files 2021-09-16 10:41:05 +02:00
Michal Sieron
a6094fd418 Move libbase/console.c logic to libc/iob.c 2021-09-16 10:41:05 +02:00
Michal Sieron
768961ec59 Use getchar/putchar instead of readchar/base_putchar 2021-09-16 10:41:05 +02:00
Michal Sieron
ead3f8b2e0 Compile iob.c with $(compile) 2021-09-16 10:41:05 +02:00
Michal Sieron
8a38a79967 Remove unnecessary headers 2021-09-16 10:41:05 +02:00
Michal Sieron
10927691c5 Remove base and add picolibc to include search paths 2021-09-16 10:41:05 +02:00
Michal Sieron
19966edb61 Replace putsnonl(s) with fputs(s, stdout)
It won't compile, because stdout is undefined, but
including headers from picolibc should fix that
2021-09-16 10:41:05 +02:00
Michal Sieron
acf3a4570b Create __iob for picolibc
Picolibc requires __iob array for its IO functions

This commit creates such array with dummy functions
using putchar/readchar from console.c

To prevent name conflicts printf and others were
removed from console.c

Also putchar had to be renamed to base_putchar
2021-09-16 10:41:05 +02:00
Michal Sieron
db390537a9 Compile entire picolibc
It does not compile yet, will need __iob array to be defined
Also there are multiple definitions of some functions
2021-09-16 10:41:05 +02:00
Michal Sieron
6de59bdbc0 Incorporate picolibc into the build process
Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command

Tested with digilent_arty.py
2021-09-16 10:41:05 +02:00
Michał Sieroń
e25ca4082b Apply patch removing need for most of libbase 2021-09-16 10:41:05 +02:00
enjoy-digital
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
George Hilliard
91ec6e0da8 clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs.  Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
George Hilliard
6733a3e3e6 clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search 2021-09-15 00:07:43 -05:00
Florent Kermarrec
88d302d4db soc/alloc_region: Ensure allocated Region is aligned on size. 2021-09-14 18:08:07 +02:00
Florent Kermarrec
694878a35a integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
Leon Schuermann
8670ac4902 litex_sim: add optional GPIOTristate core
Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 12:33:41 +02:00
Florent Kermarrec
cb7b0f44cf tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
Leon Schuermann
af8459301c litex/soc/cores/gpio: support external tristate buffer
Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 11:17:54 +02:00
Camilo Andres Vera Ruiz
a235eaf0cd
Linker fix for initialized global variables
I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
2021-09-13 00:44:30 -05:00
Stafford Horne
ea06948c62 json2dts_linux: Add configuration for root device
This allows setting a root device other than ram0, this is useful
when using a rootfs from the SD card.  Doing this makes boot time
faster and saves on memory footprint used by an in ram initrd.
2021-09-12 14:44:22 +09:00
Stafford Horne
ec2f2a6af5 json2dts_linux: Use liteuart earlycon
Now that liteuart earlycon is upstream we can use it.  This means
all litex soc's should be able to get an earlycon now.  Tested on
mor1kx.
2021-09-12 14:42:52 +09:00
Stafford Horne
378d129c5f json2dts_linux: Allow disabling of initrd 2021-09-12 14:42:46 +09:00
Leon Schuermann
6cacdcd926 {Dep,p}acketizer: handle transactions of a single bus word 2021-09-09 16:36:21 +02:00
Leon Schuermann
2e8586a090 {Dep,P}acketizer: properly handle last_be wraparound
While the Depacketizer did correctly calculate a new last_be value for
the data with the header removed, it may happen that the last_be
overflows and thus relates to the current, non-delayed sink value. The
same goes for the Packetizer, just inversed. This introduces logic in
form of a simple FSM to handle these cases and properly output last_be
on the last valid bus word.

Co-authored-by: David Sawatzke <d-git@sawatzke.dev>
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-09 16:08:12 +02:00
Nathaniel R. Lewis
ab3d7e86f2 litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe 2021-09-08 18:06:12 -07:00
Florent Kermarrec
e0e9311ceb interconnect/wishbone: Specify Wishbone version (#999). 2021-09-08 17:33:01 +02:00
Florent Kermarrec
6c2bc02323 build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
This makes it similar to add_platform_command and add more flexibility to constraint the design.
2021-09-08 16:14:58 +02:00
Florent Kermarrec
0222697f21 liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size.
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.

This will be less accurate but will still provide representative results which
is the aim of this test.
2021-09-08 09:10:21 +02:00
Florent Kermarrec
10c4523c32 soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY. 2021-09-07 15:09:05 +02:00
Florent Kermarrec
575af6fc60 litespi/integration: Review/Cleanup #1024.
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
2021-09-07 14:36:13 +02:00
enjoy-digital
aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor
litex: adding litespi to simulation, making litespi compatible with new implementation
2021-09-07 13:17:40 +02:00
wuhanstudio
5d9880888c fix: missing colon syntax error 2021-09-07 11:21:41 +01:00
Florent Kermarrec
a6f9ac58bb build/sim/common: Review/Cleanup #1021 for consistency with other backends. 2021-09-07 09:44:43 +02:00
enjoy-digital
2b700057b7
Merge pull request #1021 from antmicro/ddr_sim
litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
2021-09-07 09:38:14 +02:00
Florent Kermarrec
7c50f52a57 tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets.
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
2021-09-07 09:27:51 +02:00
enjoy-digital
1598b5958d
Merge pull request #1017 from asadaleem-rs/master
customize main ram size from command line argument
2021-09-07 09:15:55 +02:00
Florent Kermarrec
e257d91d46 cpu/vexriscv: Review/Cleanup #1022.
Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
2021-09-07 09:04:47 +02:00
enjoy-digital
6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache
Restructure config flags for dcache/icache presence in Vex.
2021-09-07 08:46:03 +02:00
Tim Ansell
bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes
Binutils fixes
2021-09-06 17:16:56 -07:00
Pawel Sagan
ad0fcc22e6 litex: adding legacy mode for litespi
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
2021-09-03 09:42:41 +02:00
Florent Kermarrec
fa5fd765a4 interconnect/packet: Add dummy to omit list, fixes #1018. 2021-09-02 18:02:16 +02:00
Florent Kermarrec
7bd06d178f cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV). 2021-09-02 15:12:16 +02:00
Pawel Sagan
3cf6126663 litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate 2021-09-02 14:33:16 +02:00
Piotr Binkowski
25e0153dd5 litex_sim: use flash model in simulation 2021-09-02 14:33:16 +02:00
Pawel Sagan
837de615e6 liblitespi: adjusting code to oddr/iddr litespi implementation
Changing litespi registers configuration to be compatible
with a new implementation.
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:33:11 +02:00
Pawel Sagan
0c91bb7b96 litex_sim: adding spi-flash option to simulation
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:22:34 +02:00
Florent Kermarrec
8c50366d15 litespi/spiflash: Use shorted message when first SPI Flash block is erased and freq test cannot be done. 2021-09-02 11:26:56 +02:00
Florent Kermarrec
103b108ea8 soc/add_spi_flash: Pass device to LiteSPIPHY for proper clk primitive instantiation. 2021-09-02 11:26:15 +02:00
Leon Schuermann
339fabf615 litex/soc: support model-version of GMII PHY in add_ether{net,bone}
This not only tests for the precise PHY model, but also whether there
is a model attribute in the ethphy instance and whether that is set to
True.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:44:55 +02:00
Leon Schuermann
2852e80eae tools/litex_sim: split out construction of ethphy
The different branches each constructed their own ethphy. We can split
this out, which increases code reuse and allows to use the GMII and
XGMII interface types with all of Ethernet, Etherbone or
Ethernet+Etherbone.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:44:55 +02:00
Leon Schuermann
08a14e8cf1 litex_sim: add GMII verilator module and add support in litex_sim
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:44:50 +02:00
Leon Schuermann
7b533a032d litex_sim: rewrite XGMII verilator module and add support in litex_sim
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:44:45 +02:00
Leon Schuermann
92ceb8f73d litex_sim: rename clk_edge to clk_edge_state, add clk_edge enum
This renames the `clk_edge_t` struct to `clk_edge_state_t`, given it
only tracks the previous clock edge state.

Furthermore introduce a new `enum clk_edge` (typedef'd to
`clk_edge_t`) which represents all possible clock edges and add a
function (`clk_edge`) to retrieve the type of current clock edge as a
`clk_edge_t`.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-01 20:44:41 +02:00
Tim Callahan
ca563dd5f3 Restructure config flags for dcache/icache presence in Vex.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-09-01 11:24:44 -07:00
enjoy-digital
315fbe18cb
Merge pull request #1016 from antmicro/jboc/lpddr5
soc/software/liblitedram: fix max error count computation
2021-09-01 11:16:07 +02:00
Florent Kermarrec
feeb2bfe31 tools/litex_contributors: Add special cases for companies to replace individuals with company name/email.
Avoid doing it manually.
2021-09-01 11:09:26 +02:00
Joel Stanley
722772a3d8 microwatt: Fix relocation error when linking
When building with GCC 11:

../libbase/crt0.o: in function `_start':
litex/soc/cores/cpu/microwatt/crt0.S:54:(.text+0x38): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:55:(.text+0x3c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_edata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:56:(.text+0x40): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata_rom' defined in *ABS* section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:68:(.text+0x68): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fbss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:69:(.text+0x6c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_ebss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:80:(.text+0x90): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fstack' defined in .bss section in bios.elf
boot.o: in function `copy_file_from_sdcard_to_ram':
litex/soc/software/bios/boot.c:622:(.text+0x18): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'
litex/soc/software/bios/boot.c:627:(.text+0x5c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+8
litex/soc/software/bios/boot.c:633:(.text+0x8c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+10
litex/soc/software/bios/boot.c:639:(.text+0xdc): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+18
litex/soc/software/bios/boot.c:650:(.text+0x128): additional relocation overflows omitted from the output

This is because we pass -mcmodel=small. As the PowerPC ELF ABI
describes, the small code model restricts the relocations to 16-bit
offsets[1]. If we omit the option we get the default, which is the
medium model allowing 32-bit offsets.

http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/dbdoclet.50655240_19143.html

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 18:02:19 +09:30
Pawel Sagan
8aa7c1b9dd litex: adding oddr/iddr/ddrtristate simulation models
Signed-off-by: Pawel Sagan <psagan@antmicro.com>
2021-09-01 10:25:21 +02:00
Joel Stanley
d91c8dcfa2 bios: Fix build-id link error
New version of binutils contain stricter checks for sections that are
not included in the linker script, resulting in this error:

 ld: error: no memory region specified for loadable section `.note.gnu.build-id'

Disable this feature as there is no use for it on bare metal systems.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 15:41:24 +09:30
Joel Stanley
c74e3642b3 bios: Fix PHDR link error
binutils 2.34 contains stricter checks for sections that are not
included in the linker script, resulting in this error:

 ld: bios.elf: error: PHDR segment not covered by LOAD segment

From the 2.34 NEWS:

  The ld check for "PHDR segment not covered by LOAD segment" is more
  effective, catching cases that were wrongly allowed by previous versions of
  ld.  If you see this error it is likely you are linking with a bad linker
  script or the binary you are building is not intended to be loaded by a
  dynamic loader.  In the latter case --no-dynamic-linker is appropriate.

As the BIOS runs bare metal, we do not need to emit a PHDR segment.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 15:33:44 +09:30
asadaleem-rs
8428e89f09 customize main ram size from command line argument 2021-08-30 17:36:40 +05:00
Jędrzej Boczar
f943092bb5 soc/software/liblitedram: fix max error count computation
READ_CHECK_TEST_PATTERN_MAX_ERRORS was being computed incorrectly
which could result in integer underflows when computing core via
(max_errors - errors). This could happen e.g. when using
DFIRateConverter, which modifies DFII_PIX_DATA_BYTES. Now we use
DFII_PIX_DATA_BYTES in the equation so this should not happen.
2021-08-30 12:54:49 +02:00
enjoy-digital
1d27e25cbb
Merge pull request #1015 from antmicro/ddr-tristate
build: add DDRTristate
2021-08-27 19:12:45 +02:00
Piotr Binkowski
84896f73ac build: add DDRTristate 2021-08-27 13:51:58 +02:00
enjoy-digital
53750715d7
Merge pull request #1013 from antmicro/reset-tx-uart-pad
Set TX UART pin high on reset
2021-08-26 18:54:18 +02:00
Michal Sieron
47291e07f7 Set TX UART pin high on reset
Without this we get corrupted data on the output after
SoC reset. It was present there, but got removed in
908e72e65b refactor.
Fixes #991
2021-08-26 18:07:03 +02:00
Gabriel Somlo
98a0b688bf json2dts_linux: update ethmac DT node generation
The Linux LiteETH driver parses registers by name. Provide the expected
names for each register: "mac", "mdio", and "buffer", respectively.

For setting up tx and rx slots, the Linux driver expects three pieces
of information: number of tx and rx slots, and slot size. Update
json2dts_linux to provide the appropriate names and values.
2021-08-25 17:51:23 -04:00
Florent Kermarrec
f017b06926 integration/export/get_csr_json: Only set type to "ro" for read_only CSRStatus. 2021-08-24 19:26:36 +02:00
Florent Kermarrec
05a614c7a2 integration/export: Cosmetic cleanups. 2021-08-24 19:13:16 +02:00
Florent Kermarrec
44b223a918 soc/integration/builder: Force a fresh software build when variables.mak is changing.
When playing with CPUs and variants, users previously had to do a rm -rf build to ensure
a proper software build. Various developers already lost time on it so it's important
to handle it directly in the Builder which is now the case.
2021-08-24 15:38:42 +02:00
Florent Kermarrec
dceed5f7e7 tools: Rename JSON based generators and expose new ones:
-litex_json2dts_linux  (previously litex_json2dts).
-litex_json2dts_zephyr (previously litex_zephyr_dts_generator).
-litex_json2renode     (previously litex_renode_generator).

litex_json2dts_zephyr and litex_json2renode are now also directly exposed.
2021-08-24 08:52:56 +02:00
enjoy-digital
d0b2eec962
Merge pull request #993 from antmicro/add_renode_scripts
Add Renode platform/script and Zephyr DT overlay generators
2021-08-24 08:45:22 +02:00
enjoy-digital
17a7ac19b6
Merge pull request #986 from antmicro/jboc/lpddr5
soc/software/liblitedram: fix pattern checking for low DFI databits
2021-08-23 19:11:18 +02:00
Florent Kermarrec
babbcd28bc software: Review/Cleanup #998.
- Fix compilation in sdram.c.
- Fix warnings.
- Move Sequential/Random mode printf to memtest.
- Reduce SPI Flash test size (Testing full SPI Flash makes the boot too long, especially in random mode).
2021-08-23 17:59:11 +02:00
Florent Kermarrec
b50d5aa328 Merge branch 'memspeed-ra' of git://github.com/antmicro/litex into antmicro-memspeed-ra 2021-08-23 17:02:58 +02:00
enjoy-digital
16f6f08d00
Merge pull request #1004 from antmicro/liblitespi-freq-init
liblitespi: perform frequency initialization after entering quad/qpi mode
2021-08-23 16:36:42 +02:00
Michal Sieron
2883187c48 Make sure crt0 files come first
BIOS jumps on boot to the beginning of main_ram.
Unless `_start` function of loaded binary is there
it won't work correctly.
2021-08-19 15:05:11 +02:00
Michal Sieron
92fd154b28 Fix alignments in demo/linker.ld
Without this change, when `.data` section size wasn't multiple
of word size, `data_loop` in crt0 was jumping over `_edata` and
continued looping. As it works on words and right now 64 bit CPUs
are biggest ones supported - alignment is now 8 bytes.

Also removed `- 4` from stack address, as it needs to be aligned
to 16 bytes on RISC-V.
2021-08-18 18:25:22 +02:00
Filip Kokosinski
ebc4ddc1e5 soc: software: liblitespi: enter quad mode before freq init
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-08-16 07:47:08 +02:00
enjoy-digital
20e910b836
Merge pull request #995 from david-sawatzke/ecpprog
Add ecpprog-based programmer for ecp5
2021-08-13 12:19:26 +02:00
David Sawatzke
9b8253c016 build/lattice/programmer: Add ecpprog-based programmer 2021-08-13 11:14:07 +02:00
enjoy-digital
17b8a74735
Merge pull request #994 from antmicro/fix-clang-support-detection
Fix clang support detection
2021-08-13 10:21:13 +02:00
Florent Kermarrec
e3a88c324e cpu/rocket/blackparrot: Update crt_init (#988). 2021-08-13 10:16:43 +02:00
enjoy-digital
601e96e5d1
Merge pull request #988 from antmicro/fix-longlong
Fix stack alignment
2021-08-13 09:59:19 +02:00
Filip Kokosinski
27f73533b9 soc: software: add random_access option to memspeed
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-08-12 09:05:09 +02:00
Christian Klarhorst
ebe22ca2b6 cores/vexriscv_smp: Fix vexriscv_smp doesn't build without a memory bus
The current code only works with a memory bus because otherwise
"generate_cluster_name" doesn't get called.
Cluster_name is only needed in the finalize phase.
Therefore, the name will now be generated just before its usage.

Verifiable with: 
litex_sim --cpu-type vexriscv_smp (should be broken before this commit)
2021-08-11 14:17:58 +02:00
Michal Sieron
d1e70498a6 Fix clang support detection 2021-08-11 11:39:31 +02:00
Mateusz Holenko
fcbebde302 Add Zephyr DTS overlay generator 2021-08-11 11:27:28 +02:00
Mateusz Holenko
d9c67dd763 Add Renode scripts generator 2021-08-11 11:27:28 +02:00
Michal Sieron
8c2e13bff7 Fix stack alignment
RISC-V requires stack to be aligned to 16 bytes.
1d5384e669/riscv-elf.md (L183)

Right now, in bios/linker.ld, `_fstack` is being set to 8 bytes
before the end of sram region.
```
PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 8);
```

Removing ` - 8` makes it aligned to 16.

Also there are changes in crt0.S for vexriscv,
vexriscv_smp and cv32e40p.

Code that was setting up stack, was adding 4 to its address
for some reason.

Removing it makes it aligned to 8 bytes, and with change in
bios/linker.ld to 16 bytes.

It also fixes `printf` with long long integers on 32bit
CPUs ([relevant issue](https://github.com/riscv/riscv-gcc/issues/63)).
2021-08-10 13:00:46 +02:00
Dan Callaghan
cd8666d0b3 build/lattice: work around lack of SDR I/O primitives in nextpnr
Fixes #907.
2021-08-09 19:26:40 +10:00
Florent Kermarrec
79ac09316a interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case. 2021-08-06 16:41:58 +02:00
Jędrzej Boczar
6f8a0052ef soc/software/liblitedram: fix pattern checking for low DFI databits 2021-08-04 15:14:07 +02:00
Florent Kermarrec
ce5864983d soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case.
A regular CPU can provides specific mapping constraints and we are overriding provided mapping
with these constraints.

The case of CPUNone is different and we can do the opposite: Give priority to User's mapping.

For the regular CPU case, the override was done silently, it is now logged during the build.
2021-07-30 15:00:10 +02:00
Florent Kermarrec
c80d5723c9 soc/add_spi_flash: Reduce default_divisor. 2021-07-30 12:32:57 +02:00
Florent Kermarrec
6100620634 bios/main: Display Flash in SoC capabilities. 2021-07-29 19:26:01 +02:00
Florent Kermarrec
518a3e1f65 liblitespi/spiflash: Use software defined constants and fix spiflash_master_write (mmap renamed to core). 2021-07-29 19:25:28 +02:00
Florent Kermarrec
ab48461d6a soc/add_spi_flash: Generate useful software constants from SPIFlash module. 2021-07-29 19:24:30 +02:00
Florent Kermarrec
f0a258e0a7 soc/add_spi_flash: Use cached SoCRegion, fixes #981. 2021-07-29 18:53:04 +02:00
Florent Kermarrec
bb9701b5f6 soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py. 2021-07-29 18:48:03 +02:00
Florent Kermarrec
60c4a1b667 liblitespi/spiflash: Review #979 and other cleanups.
- Rename optional #define and allow defining them externally.
- Add comments.
- Rename FLASH_CHIP_MX25L12833F_QUAD to SPIFLASH_MODULE_QUAD_CAPABLE.
- Rename FLASH_CHIP_MX25L12833F_QPI  to SPIFLASH_MODULE_QPI_CAPABLE.

The instructions used for QUAD/QPI are probably different between chips, we could
imagine providing them through the LiteX integration based on the passed SPI Flash
module.
2021-07-29 18:21:07 +02:00
enjoy-digital
1933beadb1
Merge pull request #979 from antmicro/litespi-qpi
WIP: enable QPI mode in liblitespi
2021-07-29 17:59:51 +02:00
Florent Kermarrec
c5b5abd103 soc/add_spi_flash: Rename spiflash_mmap to spi_flash_core (since LiteSPI inclule MMAP and Master Interface). 2021-07-29 17:42:07 +02:00
Florent Kermarrec
505c8b85d6 soc/add_spi_flash: Reduce LiteSPIPHY default divisor to max(2, self.sys_clk_freq/clk_freq).
One small FPGAs running the BIOS from SPI Flash, the default divisor of 9 was slowing down too
much BIOS boot time (It was OK on reboot after liblitespi auto-calibration). Reduce the default
divisor to avoid this.
2021-07-29 17:16:47 +02:00
Florent Kermarrec
14d60661b9 software/bios/main: Generate Initialization banner for SPIFlash. 2021-07-28 10:55:02 +02:00
Florent Kermarrec
8415e5d6ac integration/soc/add_spi_flash: Add LiteSPI initial support (enabled when module is provided).
Test on iCEBreaker in 1X/4X mode for now. In the future, we could probably deprecate support
for old SPIFlash core.
2021-07-27 19:21:54 +02:00
Florent Kermarrec
80e9d2cea9 soc/interconnect/stream: Support n=1 case on Multiplexer/Demultiplexer.
Required by LiteSPI when only one Core is connected to the PHY (ex when disabling Master or MMAP).
2021-07-27 16:57:22 +02:00
developandplay
c36e2ae4e8 Add imafd support 2021-07-27 00:44:32 +02:00
developandplay
6ba514ee96 Separate BlackParrot code from adapter code 2021-07-27 00:43:09 +02:00
enjoy-digital
3387853b6b
Merge pull request #977 from antmicro/jboc/gtkw-endpoint
GTKWSave: improved support for Endpoint
2021-07-26 15:01:49 +02:00
Filip Kokosinski
0a0e337754 soc: software: liblitespi: enter QPI mode when using MX25L12833F 2021-07-26 14:32:56 +02:00
Florent Kermarrec
1ce48a973b clock/lattice_ecp5: Fix and rework 4-output solver implementation.
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
Jędrzej Boczar
4636a841d3 build/sim/gtkwave: automate handling of Endpoint and other stream primitives 2021-07-22 15:49:20 +02:00
enjoy-digital
751e99690e
Merge pull request #965 from thirtythreeforty/ecp5-pll-x4
ECP5PLL: implement 4-output solver
2021-07-21 19:08:18 +02:00
Christian Klarhorst
e17a010866 soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode 2021-07-20 22:08:36 +02:00
Florent Kermarrec
c64c6e4056 cpu/blackparrot: Re-map csr and keep the lower 128MBs for the SoC IO auto-allocation. 2021-07-20 12:05:54 +02:00
Gwenhael Goavec-Merou
e3f577e0be openfpgaloader: improves freq conversion type 2021-07-17 17:02:22 +02:00
Florent Kermarrec
e0d5a7bff5 interconnect/packet/Packetizer/Depacketizer: Avoid generating unaligned logic when aligned. 2021-07-15 19:00:50 +02:00
Florent Kermarrec
0a919e709f interconnect/packet: Improve PacketFIFO to handle payload/param separately.
Useful to save resources and store Stream's params more efficiently.
2021-07-15 18:06:03 +02:00
Florent Kermarrec
b2f8fa5464 gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
enjoy-digital
bf52c1083f
Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_options
openfpgaloader: add cable and freq options
2021-07-15 12:18:01 +02:00
Florent Kermarrec
730b57d9cd build/gowin: Add initial timing constraints support. 2021-07-15 11:06:03 +02:00
Florent Kermarrec
10ea45da55 build/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl. 2021-07-15 10:01:52 +02:00
Florent Kermarrec
2b393254da build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed).
Most of the attributes are Xilinx specific, it does not make sense to provide them on other FPGA devices.
2021-07-15 09:59:15 +02:00
Florent Kermarrec
bdc32171fd gen/fhdl/verilog/_printattr: Avoid trying translating attribute when not supported by Toolchain. 2021-07-15 09:57:15 +02:00
Florent Kermarrec
4fd974be10 build/gowin: Minor cleanups. 2021-07-15 09:36:41 +02:00
Gwenhael Goavec-Merou
3706ed7416 openfpgaloader.py: cast int to str 2021-07-14 17:50:50 +02:00
Gwenhael Goavec-Merou
c984a4dbc8 openfpgaloader: add cable and freq options 2021-07-14 16:48:29 +02:00
Florent Kermarrec
756503ab92 clock/gowin_gw1n: Add Initial On-Chip Oscillator support.
Ex: self.submodules.osc = GW1NOSC(device="GW1N9K", freq=10e6)
2021-07-14 11:42:35 +02:00
Florent Kermarrec
6fc87f7c85 build/gowin/common: Add DDRInput/DDROutput implementations. 2021-07-14 10:01:54 +02:00
Florent Kermarrec
a8cea15b95 cores/clock/gowin_gw1n/create_clkout: Add reset support (through AsyncResetSynchronizer) and enable it by default.
Should be based on PLL's lock but does not seem stable, so use reset input for now.
2021-07-14 09:38:23 +02:00
Florent Kermarrec
cfbc06c297 build/gowin/common: Add AsyncResetSynchronizer implementation. 2021-07-14 09:37:00 +02:00
enjoy-digital
fab6512928
Merge pull request #967 from JosephBushagour/jbushagour_assembly_interoperability
Make "generated/soc.h" able to be included in assembly files.
2021-07-13 10:47:59 +02:00
enjoy-digital
df67b65a0a
Merge pull request #957 from pftbest/fix_fst
Fix compile error when FST traces are enabled on macOS.
2021-07-13 10:38:40 +02:00
Joey Bushagour
c79e428fe1 Add soc.h interoperability with assembly. 2021-07-12 08:33:17 -05:00
Florent Kermarrec
bc77aa37f0 include/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
- Shift in _csr_rd_buf should only been done when buf is set.
- When CSR size is not an exact multiple of the CSR data-width, the gap is in
the low addresses, not the high ones. So offset is introduced to take this into
account.
2021-07-09 17:36:17 +02:00
Florent Kermarrec
b29a99cd0b liblitedram/sdram.c: Fix DFII_PIX_DATA_BYTES computation.
DFII CSR size is not necessarily multiple of 4 (often the case but not with ECC for example).
2021-07-09 17:32:43 +02:00
George Hilliard
8954041a93 clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this.  Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
Florent Kermarrec
9a51dfb50e tools/litex_sim: Let the SDRAMPHYModel pick default settings. 2021-07-08 09:09:57 +02:00
Florent Kermarrec
fced79631e tools/litex_sim: sdram_module_nphases/get_sdram_phy_settings now directly integrated in litedram.phy.model. 2021-07-08 09:01:32 +02:00
George Hilliard
34ba649f38 clock/lattice_ecp5/ECP5PLL: implement 4-output solver
Reimplement the configuration loop to allow all 4 outputs to be used by
the user, if one of them is suitable for use as VCO feedback.

The new strategy is to first iterate over requested outputs to see if
any of them can be used as a feedback source.  If one can, it is
selected, and if no output is suitable, it attempts to instantiate one.
Once the feedback path is selected, the VCO frequency is known and it
attempts to calculate the remaining outputs' settings.

In addition, this implementation now respects datasheet limits in two
new ways:

- It respects the post-input-divider minimum frequency of 10MHz
- It respects the max output frequency of 400MHz for instantiated
  feedback outputs

I am slightly unhappy with the seemingly-repetitive for loops. However
each one has slightly different sematics and I don't see a way to
combine them that doesn't hinder readability.
2021-07-07 01:15:06 -05:00
George Hilliard
8b9f03efba clock/lattice_ecp5/ECP5PLL: Expose standby signal 2021-07-06 08:40:36 -05:00
Yoshimasa Niwa
0953c52eea Increase delay for tty.usbmodem on macOS.
**Problems**

On macOS USB CDC ACM, which appears as `/dev/tty.usbmodem*`,
somehow `lxterm` keeps failing to send a payload.

**Solution**

Increase delay.

It's very unknown why to me, however, probably macOS USB CDC ACM
driver implementation issue.

**Testing**

Tested on MacBook Air (2020, M1) for OrangeCrab (rev.0.2) target
with Linux on LiteX SoC bitstream build from current commit and
load prebuild Linux On LiteX image.
2021-07-05 11:46:57 -07:00
Florent Kermarrec
f9f1b8e25d liblitedram: Consider 1s window is valid when indirectly seen before 0 (start at 0 and long enough). 2021-06-29 12:03:51 +02:00
Ilia Sergachev
65babd6500 soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite 2021-06-28 11:50:45 +02:00
Vadzim Dambrouski
35204225e8 Fix compile error when FST traces are enabled on macOS.
Compile options should be the same for all platforms.
2021-06-27 17:34:43 +03:00
developandplay
9fd9eaea07 Move patch script to python-data 2021-06-27 01:31:05 +02:00
developandplay
ac217d818f Set environmental variables in python 2021-06-27 01:07:27 +02:00
developandplay
e3f6d8349b Use os methods to expand env vars 2021-06-26 16:30:54 +02:00
developandplay
b787ee4411 Move systemverilog files to python-data 2021-06-26 15:45:48 +02:00
developandplay
16b3e08c17 Copy config loader in python 2021-06-26 15:37:17 +02:00
enjoy-digital
23afca3de8
Merge pull request #953 from developandplay/blackparrot-32bit-csr
Blackparrot 32bit csr
2021-06-23 19:20:51 +02:00
Florent Kermarrec
edc4c85615 build/lattice/common: Add ECP5 Differential Output support. 2021-06-23 11:55:22 +02:00
developandplay
adb71bde8c Adjust wishbone adapter for 32bits 2021-06-22 23:37:24 +02:00
developandplay
b795f848a2 Fixup blackparrot 2021-06-22 18:43:17 +02:00
Florent Kermarrec
c395a8068a cores/prbs: Minor Cleanup and make sure to generate errors when RX is Idle. 2021-06-22 16:57:00 +02:00
Florent Kermarrec
2cd6224acf clock/lattice_ecp5/ECP5PLL: Add expose_dpa method (Dynamic Phase Adjustment) and move code to it. 2021-06-22 12:07:39 +02:00
enjoy-digital
09a3ca6fd0
Merge pull request #949 from zyp/ecp5_dynamic_pll
cores/clock/ecp5: Add dynamic phase adjustment signals.
2021-06-22 12:04:20 +02:00
enjoy-digital
26df3fa2c4
Merge pull request #952 from smunaut/dfu
build/DFUProg: Allow to specify alt interface and to not reboot
2021-06-22 12:03:43 +02:00
Florent Kermarrec
3d81c9a437 build/lattice/LatticeProgrammer: pgrcmd always seems to return a non-zero value so disable check. 2021-06-22 11:59:42 +02:00
Florent Kermarrec
f381cdcd1a build/GenericProgrammer: Add check parameter to make check optional. 2021-06-22 11:59:38 +02:00
Sylvain Munaut
38e46bb3d3 build/DFUProg: Allow to specify alt interface and to not reboot
Some targets have multiple alt settings for DFU for different zone
of the flash. Allowing to specify which one to flash and not
rebooting immediately allows to flash several of them at once.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 16:12:55 +02:00
Florent Kermarrec
d6f24f2f68 cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40. 2021-06-20 14:33:25 +02:00
Florent Kermarrec
4c8184fbb6 cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt. 2021-06-20 08:58:45 +02:00
Vegard Storheil Eriksen
b58c416a24 cores/clock/ecp5: Add dynamic phase adjustment signals. 2021-06-19 11:24:08 +02:00
developandplay
7d2e19ac26 Enable non-interactive mode 2021-06-18 12:35:42 +02:00
enjoy-digital
fdb278838c
Merge pull request #881 from developandplay/patch-1
Add --non-interactive option to simulation
2021-06-18 10:40:19 +02:00
Florent Kermarrec
5205356d24 tools/litex_json2dts: Simplify Switches interrupt support (and make it similar to other interrupts). 2021-06-18 10:36:33 +02:00
enjoy-digital
291374e66f
Merge pull request #854 from mczerski/gpio_dts_irq
dts: gpio: interrupt controller definition for switches
2021-06-18 10:29:30 +02:00
Florent Kermarrec
98676162a3 VexRiscv-SMP: Review/Cleanup #906. 2021-06-18 10:19:27 +02:00
enjoy-digital
58c533668c
Merge pull request #906 from rdolbeau/extra_config_and_dts
Configurable [ID]TLB for VexRiscv & improved DTS
2021-06-18 10:09:28 +02:00
Florent Kermarrec
8ce7c583e6 cores/spi: Add Manual CS Mode (to allow doing Bulk Xfers without external changes), also cleanup/simplify a bit CSR descriptions. 2021-06-18 10:07:01 +02:00
Florent Kermarrec
a4be067d91 tools: Add litex_contributors.py script to easily update CONTRIBUTORS file. 2021-06-17 23:04:28 +02:00
Florent Kermarrec
7179d88e8c ram/lattice_nx: Add init parameter and rename method to add_init.
When init is not empty, call add_init automatically (similar to Memory).
2021-06-16 18:33:00 +02:00
enjoy-digital
869b5c24a8
Merge pull request #941 from danc86/nxlram-initval
soc/cores/ram: allow populating initial values in Nexus LRAM
2021-06-16 18:31:00 +02:00
enjoy-digital
b0e6851150
Merge pull request #942 from zyp/external_software_packages
Allow external software packages to be linked into the BIOS
2021-06-16 18:21:55 +02:00
enjoy-digital
aad64bbf9b
Merge pull request #943 from JosephBushagour/jbushagour_getargspec_fix
Replace deprecated inspect.getargspec with inspect.getfullargspec.
2021-06-16 14:59:39 +02:00
Tim Callahan
e59530ab50 Force SymbiFlow 'make' to be non-parallel.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-06-15 14:49:28 -07:00
Florent Kermarrec
8a644c9086 soc/add_video_xy: Allow passing phy or phy's Endpoint. 2021-06-15 18:10:24 +02:00
Joey Bushagour
62ea48940a Replace deprecated inspect.getargspec with inspect.getfullargspec. 2021-06-15 08:03:11 -05:00
Vegard Storheil Eriksen
8d527a1f3f soc/software/bios: Allow registering init functions. 2021-06-13 14:04:34 +02:00
Vegard Storheil Eriksen
61636f1248 soc/integration/builder: Allow linking in external software packages. 2021-06-13 14:04:34 +02:00
Dan Callaghan
be4c7cfb34 soc/cores/ram: allow populating initial values in Nexus LRAM
On designs which use Nexus parts without any external memory, it can be
difficult to fit an embedded ROM program larger than a few KiB. Radiant
cannot infer LRAM, and refuses to infer EBRAM under many circumstances
too, so large memories tend to just consume a huge number of LUTs.

This patch makes it possible to explicitly wire up an LRAM as a ROM,
populate its initial values with a program, and execute directly from
it. That lets us embed programs up to 64KiB.
2021-06-11 16:41:10 +10:00
bunnie
311b633a11 breakout the keyclearb pin for integration elsewhere 2021-06-11 04:44:39 +08:00
enjoy-digital
0a932be491
Merge pull request #936 from developandplay/patch-4
Sync ROM_BOOT_ADDRESS with main_ram location
2021-06-09 12:11:24 +02:00
enjoy-digital
d5cfe09f4c
Merge pull request #931 from madscientist159/add-1920-1200-mode
Add 1920x1200@60 RBv2 to LiteX video modes
2021-06-09 09:03:57 +02:00
enjoy-digital
8cdb0b8db3
Merge pull request #932 from developandplay/patch-3
Fix base_address for LiteDRAMWishbone2Native
2021-06-09 08:58:28 +02:00
Florent Kermarrec
5061a368da cores/video: Regroup VGA/DVI Phy in VideoGenericPHY and support variations (positive/negative hsync/vsync, etc...) 2021-06-09 08:49:29 +02:00
developandplay
e0352a1f0f
Sync ROM_BOOT_ADDRESS with main_ram location
Rocket and Blackparrot main_ram starts at 0x80000000
Vexriscv main_ram starts at 0x40000000
2021-06-09 03:36:32 +02:00
Florent Kermarrec
25ead1ad69 interconnect/stream: Add Gate. 2021-06-08 18:58:08 +02:00
developandplay
f2caeaf83a
Fix base_address for LiteDRAMWishbone2Native
Fixes `origin == None` due to https://github.com/litex-hub/litex-boards/commit/ba01776
2021-06-08 00:51:11 +02:00
Raptor Engineering Development Team
47c19933fa Add 1920x1200@60 RBv2 to LiteX video modes Tested on Raptor Sparrowhawk 2021-06-07 14:49:33 -05:00
Florent Kermarrec
a064e9d048 soc/interconnect/wishbone: Fix SEL propagation on UpConverter (thanks @Dolu1990). 2021-06-02 10:46:53 +02:00
Florent Kermarrec
0b329c3dce tools/litex_json2dts: Add initial USB OHCI support. 2021-06-01 10:41:35 +02:00
Florent Kermarrec
a17ded2ce6 soc/cores: Add initial USB OHCI core wrapper. 2021-06-01 10:28:30 +02:00
Florent Kermarrec
6c8e839cef soc/cores/freqmeter: Minor simplification. 2021-06-01 10:26:27 +02:00
Florent Kermarrec
26db10701a integration/soc/add_video_terminal: Connect UART to TX FIFO instead of Source.
Allow UART to be displayed on terminal with Auto TX flush.
2021-05-28 11:11:49 +02:00
Florent Kermarrec
ad1fe143cc cores/uart: Cleanup code and add optional automatic TX Flush.
In some SoCs where UART's PHY is managed externally (ex through a Bridge) we don't
necessarily want the UART TX to wait for the PHY to be ready (and then stall the
CPU) but just want to let the CPU print the UART and will just connect when useful
and handle backpressure when connected.

This is now possible by calling add_auto_tx_flush method, ex in the SoC:
self.uart.add_auto_tx_flush(sys_clk_freq)
2021-05-28 11:03:23 +02:00
Florent Kermarrec
d11dc0b503 libbase/memtest: Print size with 1 digit after the decimal point. 2021-05-27 19:33:29 +02:00
enjoy-digital
9b85769499
Merge pull request #923 from gsomlo/gls-fix-gcc-warn
software/lib*: address gcc warnings
2021-05-27 18:50:24 +02:00
enjoy-digital
d7f4293743
Merge pull request #924 from developandplay/patch-2
Use add_etherbone in simulation
2021-05-27 18:49:45 +02:00
Florent Kermarrec
34df454157 cores/timer/uart: Use edge="rising on Timer/UART's EventSourceProcess.
Make code easier to understand.
2021-05-27 18:47:40 +02:00
Gabriel Somlo
9a24034d1d software/lib*: address gcc warnings
Fix gcc warnings: use 'unsigned long' to represent memory addresses,
and remove 'static' from the definition of 'cdelay()', as it is called
from multiple C files.
2021-05-27 08:47:29 -04:00
developandplay
c17421bccb
Use add_etherbone in simulation
Fixes not working analyzer example from wiki
2021-05-26 23:18:22 +02:00
Florent Kermarrec
5fd215fe3a soc/interconnect/stream/Pipeline: Improve comments. 2021-05-26 18:34:22 +02:00
Florent Kermarrec
b1d8fe61f8 cores/cpu: Add initial FemtoRV support.
FemtoRV is a minimalist RISC-V CPU with design process documented and
available at https://github.com/BrunoLevy/learn-fpga.

This CPU is a very nice way to discover/learn RISC-V and this LiteX support
can be useful to learn how to integrate a custom CPU with LiteX.

With this support, FemtoRV is now directly usable with LiteX Sim:
$litex_sim --cpu-type=femtorv

This should also enable its use on all boards (> 50) available in LiteX-Boards
repository (but hasn't been tested yet), ex:
$python3 -m litex_boards.targets.digilent_arty --cpu-type=femtorv --build
2021-05-26 09:08:41 +02:00
Florent Kermarrec
d3560e5772 liblitedram/sdram.c: Update sdram_write_read_check_test_pattern with SDRAM_PHY_ECP5DDRPHY.
The return value has been changed and also required to be update for SDRAM_PHY_ECP5DDRPHY.
2021-05-25 10:28:56 +02:00
enjoy-digital
8085cc3c97
Merge pull request #915 from zyp/liblitespi_remove_mode
software/liblitespi: Remove manual mode control.
2021-05-25 08:41:13 +02:00
Romain Dolbeau
c06bd2c77d Make the [ID]TLB size configurable from Litex ; expand the DTS to include cache/TLB/topology in CPUs & generate the required information for VexRiscv 2021-05-23 03:15:02 -04:00
Florent Kermarrec
55344b4c14 cores/clock/xilinx: Add power down support. 2021-05-19 22:31:35 +02:00
Florent Kermarrec
cbb75b852e cores/clock/xilinx: Cosmetic cleanup on Instances. 2021-05-19 22:20:04 +02:00
Florent Kermarrec
12b27f961c software/liblitedram: Fix compilation on designs without SDRAM. 2021-05-19 11:07:03 +02:00
Florent Kermarrec
aa2622b1f5 software/liblitedram: Add missing #ifdef SDRAM_DEBUG to fix compilation with large DRAMs.
sdram_dbg seems to have current limitations: "At most 32 databits SDR or 16 databits DDR supported".
2021-05-18 11:36:19 +02:00
Jędrzej Boczar
93f357d853 soc/software/liblitedram: make leveling scores more robust by counting number of bitslips 2021-05-17 14:53:04 +02:00
Jędrzej Boczar
50805797c6 soc/software/liblitedram: optional write latency calibration debug output 2021-05-17 14:49:30 +02:00
Jędrzej Boczar
1f2b8621fe soc/software/liblitedram: add sdram_debug command 2021-05-17 14:38:35 +02:00
Jędrzej Boczar
e5c1482572 soc/software/liblitedram: add sdram debugging utilities 2021-05-17 14:19:16 +02:00
Jędrzej Boczar
cd6f98c4c8 soc/software/liblitedram: use updated sdram_dfii_pix_X_addr interface 2021-05-17 14:11:10 +02:00
Jędrzej Boczar
33fb48584b soc/software/libbase: add option for read retries in memtest_data 2021-05-17 13:56:31 +02:00
Jędrzej Boczar
d610c9da44 soc/software/libbase: limit number of errors printed when using MEMTEST_*_DEBUG 2021-05-17 13:53:32 +02:00
Vegard Storheil Eriksen
422c356930 software/liblitespi: Remove manual mode control. 2021-05-17 13:44:02 +02:00
Jędrzej Boczar
b90d0bd1f7 soc/software/libbase: make memtest_data more configurable, add on_error callback 2021-05-17 13:42:44 +02:00
Florent Kermarrec
13979a43b7 soc/add_cpu: Fix/Simplify CFU integration. 2021-05-17 12:04:37 +02:00
Florent Kermarrec
d0e8de077c soc/SoCController: Add separate fields for SoC and CPU resets.
As discussed in #909, in some specific cases, it can be interesting to be able
to keep the CPU in reset while the rest of the SoC is still operating (ex the
peripherals/bridges).

With theses changes, the old behaviour is preserved to do a full SoC Reset (at
the exception that writing a 1 is now mandatory) and a separate field specific
to the CPU reset is added.

The SoC Reset is a pulse (otherwise the system would be stuck in Reset) while
the CPU Reset is based on the register value (so can be pulse or hold).
2021-05-17 11:43:04 +02:00
Florent Kermarrec
06f4658174 cpu: Specify clock domain (improve readability). 2021-05-17 10:51:54 +02:00
Florent Kermarrec
78bdde0424 cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu. 2021-05-17 10:02:58 +02:00
Florent Kermarrec
a6c37df175 soc_core: Improve readability and move ROM initialization to SoCCore. (--integrated-rom-file args is also renamed to --integrated-rom-init to simplify support for str and list). 2021-05-17 09:55:28 +02:00
Florent Kermarrec
dd72b1acfe soc/add_cpu: Add **kwargs support. 2021-05-17 09:53:40 +02:00
Florent Kermarrec
298f65e78e cpu/vexriscv: Change methods' order to improve readability. 2021-05-17 08:54:53 +02:00
enjoy-digital
fc0e1440c5
Merge pull request #908 from antmicro/cfu-integration
Add CFU integration
2021-05-17 08:43:38 +02:00
zyp
1571da4989
software/liblitespi: Fix speed test. (#911)
Before this patch, the loop would finish with lowest_div either set to the first failing value
or 0 even if it succeeded with 0. Fix it so that if all tests pass, it’ll end up being -1 before
the incrementation.

This patch also skips retesting the original value. If the retest failed, lowest_div would be incremented past the original value and could potentially wrap around.
2021-05-17 08:30:38 +02:00
Robert Szczepanski
d5dab98a2c Add CFU integration 2021-05-14 09:20:58 +02:00
bunnie
53982acd9f
I2S fix: sample SYNC on the correct edge (#904)
* resolve issue #862 add description to soc.svd

The issue is that with no description provided it simply would
not put out a description tag, which breaks compatibility with
other programs.

Insert a somewhat useful default description including a timestamp
and the words "LiteX SoC".

* I2S fix: sample SYNC on the correct edge

The original Tx path implementation samples SYNC on the falling
edge, out of convenience with the fact that teh data must also
change on the falling edge.

This works OK, until you have a CODEC which has a ~40ns max
delay spec on the SYNC, and also has a slightly asymmetric
SYNC edge (the SYNC signal is also the WCLK or LRCLK depending on
which docs you read). The SYNC by spec is supposed to change
on the falling edge, and this extra delay is enough to cause
the SYNC to introduce occassional bit or frame shifts into
the audio.

This fix samples the SYNC on the rising edge, but still
changes the data on the falling edge, thus allowing for
implementations where SYNC has quite loose timings relative
to everything else (as is the case on the TLV320AIC3200)
2021-05-07 08:17:49 +02:00
Hans Baier
5fd1cae618 lattice/programmer.py: Add iCESugar programmer 2021-05-07 10:55:48 +07:00
Florent Kermarrec
34ed5672c3 tools/litex_server/litex_term: Add --jtag-chain argument. 2021-05-06 15:41:25 +02:00
Florent Kermarrec
24105f12d5 openocd/stream: Expose chain parameter. 2021-05-06 15:25:18 +02:00
Florent Kermarrec
aea1e7fb20 jtag/jtagbone: Expose chain parameter. 2021-05-06 14:58:47 +02:00
Florent Kermarrec
3ce5f3867a cores/video/VideoS7GTPHDMIPHY: Add refclk support (None, Differential or Single-Ended). 2021-05-06 10:50:29 +02:00
Florent Kermarrec
bfb90f5625 soc/cores/video: Add VideoS7GTPHDMIPHY (7-Series HDMI PHY over GTPs).
Validated on Decklink Mini 4K Monitor at 1080p60 (should allow UHD/4K), still
some fixed things, but should provide a good basis to go further...
2021-05-05 18:12:10 +02:00
Florent Kermarrec
1d21a90076 software/liblitespi: Fix compilation warning. 2021-05-03 10:34:45 +02:00
Tim Callahan
dcd13d27ef Add 'lse' as a --synth-mode option with Radiant.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-05-01 21:12:56 -07:00
enjoy-digital
fb8f45be73
Merge pull request #901 from stffrdhrn/litex-sdcard-irq
integration/soc: Wire up the sdirq to the CPU
2021-04-30 12:30:35 +02:00
Florent Kermarrec
59b968decc cores/clock/gowin_gw1n: Fix indent. 2021-04-30 12:22:59 +02:00
Florent Kermarrec
5dc3ad3b29 soc/cores/spi/SPISlave: Minor cleanup. 2021-04-30 12:16:49 +02:00
Florent Kermarrec
75bb78a413 cores/clock: Add initial Gowin GW1N PLL support.
For now limited to one output clock and not supporting phase/duty cycle adjustements.
2021-04-30 11:31:04 +02:00
Florent Kermarrec
fefc5aae66 cores/video/VideoVGAPHY: Add optional clk support.
Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync)
but require the clock.
2021-04-29 11:50:04 +02:00