55 commits

Author	SHA1	Message	Date
Florent Kermarrec	71627cf9f0	bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)	2015-06-19 08:37:16 +02:00
Florent Kermarrec	f8b1152b98	wishbone: add Cache (from WB2LASMI)	2015-06-17 15:31:49 +02:00
Florent Kermarrec	33b536e505	migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter)	2015-06-02 19:29:38 +02:00
Florent Kermarrec	d83e170872	global: more pep8 ... we will have to continue the work... volunteers are welcome :)	2015-04-13 21:33:44 +02:00
Florent Kermarrec	1051878f4c	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
Florent Kermarrec	17e5249be0	global: pep8 (replace tabs with spaces)	2015-04-13 20:07:07 +02:00
Yann Sionneau	ee928a8973	Wishbone DownConverter: Fix sel signal	2014-11-26 19:33:12 +08:00
Florent Kermarrec	dbaeaf7833	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
Sebastien Bourdeauducq	90f0dfad63	Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator	2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq	63c1d7e4b7	New simulation API	2014-01-26 22:19:43 +01:00
Sebastien Bourdeauducq	29f7b94e37	bus/wishbone/sram: expose memory component	2013-11-24 23:43:14 +01:00
Sebastien Bourdeauducq	c5342c5b5c	bus/wishbone: style	2013-11-24 23:42:54 +01:00
Sebastien Bourdeauducq	99c53ed9e8	Better record layout parameterization mechanism	2013-10-23 12:54:50 +02:00
Sebastien Bourdeauducq	2cf6b6c768	wishbone/SRAM: fix non-32-bit bus	2013-08-26 20:32:59 +02:00
Florent Kermarrec	628fa8ce9e	wishbone : add DownConverter	2013-08-26 20:28:09 +02:00
Sebastien Bourdeauducq	6ba0d4bd0d	bus/wishbone: configurable data width	2013-07-27 22:25:07 +02:00
Robert Jördens	fe18397acc	wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)	2013-07-22 10:30:44 +02:00
Sebastien Bourdeauducq	bac62a32a9	Make memory ports part of specials ... This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.	2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	5208baada8	bus/wishbone/SRAM: support init and read_only	2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq	29b468529f	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq	51bec340ab	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq	f9acee4e68	corelogic -> genlib	2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq	49cfba50fa	New 'specials' API	2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq	3fae6c8f03	Do not use super()	2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq	280a87ea69	elsewhere: do not create interface in default param	2012-12-06 17:34:48 +01:00
Sebastien Bourdeauducq	4bcb39699b	bus/wishbone/sram: accept memories < 32 bits	2012-12-01 13:04:22 +01:00
Sebastien Bourdeauducq	523816982a	bus/wishbone: add SRAM	2012-12-01 12:59:09 +01:00
Sebastien Bourdeauducq	50ed73c937	New specification for width and signedness	2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq	fee22a4631	Remove Constant	2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq	ece786d6aa	bus/wishbone: allow specifying existing interface	2012-11-17 19:42:06 +01:00
Sebastien Bourdeauducq	8de192dfbd	x.bv.width -> len(x)	2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq	b4613d913f	bus/wishbone: remove use of deprecated multimux	2012-07-13 17:17:20 +02:00
Sebastien Bourdeauducq	8a23451237	PureSimulable	2012-06-12 17:08:56 +02:00
Sebastien Bourdeauducq	b7a84b3750	wishbone: base TargetModel class	2012-06-10 17:05:10 +02:00
Sebastien Bourdeauducq	ec501e7797	bus/wishbone: target model	2012-06-10 16:40:33 +02:00
Sebastien Bourdeauducq	f061b25a24	bus/wishbone/Tap: remove ack feature	2012-06-10 12:46:24 +02:00
Sebastien Bourdeauducq	11674242c4	Use super() instead of calling parent constructors directly	2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq	ab800fa2ed	bus: generic transaction model	2012-03-08 18:14:06 +01:00
Sebastien Bourdeauducq	0493212124	bus: simplify and cleanup ... Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups	2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq	0c214b484e	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
Sebastien Bourdeauducq	a99c2acfa8	Remove explicit bus names and rely on the new automatic namer	2012-01-27 22:20:57 +01:00
Sebastien Bourdeauducq	076c171c7b	Use meaningful class names	2012-01-20 23:07:32 +01:00
Sebastien Bourdeauducq	20425703fa	Wishbone: omit fixed LSBs	2012-01-13 17:29:05 +01:00
Sebastien Bourdeauducq	ba40f58491	corelogic: operator tree	2011-12-22 15:46:19 +01:00
Sebastien Bourdeauducq	107f03fd4b	Remove uses of declare_signal	2011-12-18 21:47:48 +01:00
Sebastien Bourdeauducq	c7b9dfc203	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq	39b7190334	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq	92f24b784d	wishbone: decoder: fix slave cyc generation in registered mode	2011-12-13 14:08:39 +01:00
Sebastien Bourdeauducq	923fc52e68	wishbone: only send ack to the active master in arbiter	2011-12-13 00:25:25 +01:00