d5723968da
Merge remote-tracking branch 'origin/master' into linux
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# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
2019-04-12 16:26:08 +02:00
13b774b535
#69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut
2019-04-12 15:56:22 +02:00
41ff87f83b
Remove jalr from decode branch prediction missaligned inibition
2019-04-12 15:27:10 +02:00
63cd5f42af
Fix #69 discoverd fmax issue with decode stage branch predictions
2019-04-12 15:24:33 +02:00
b329ee85ad
#60 Fix missing ecallGen flag
2019-04-11 15:30:54 +02:00
ece1e73547
Default linux config is now without RVC
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Remove all linux usless CSR from the config
Remove verilator instruction fetch check
2019-04-11 01:18:15 +02:00
caa37a8028
Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware)
2019-04-10 19:04:52 +02:00
6b22594961
Flush MMU line with exception on context switching instead than on cmd fire
2019-04-10 15:42:39 +02:00
d7f6c18c0a
Fix DebugPlugin -> force machine mode, force uncached memory load
2019-04-10 00:35:15 +02:00
fd42e7701e
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
2019-04-09 01:22:32 +02:00
21cb8615fd
Clean and fix things to get all the non-linux configs and machine only configs working
2019-04-08 16:06:05 +02:00
32921491b8
#60 Fix instruction cache refill
2019-04-08 14:24:37 +02:00
fd15a938c5
#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.
2019-04-08 13:20:56 +02:00
c2595273ec
Add a busy flag from MMU ports
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iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
2019-04-08 11:38:40 +02:00
f89ee0d422
#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
2019-04-07 15:44:25 +02:00
4fd36454d7
Complain about wrong earlyBranch settings.
2019-04-06 12:58:19 -07:00
39a4aa5e26
GenMicroNoCsr: no memory stage, no write-back stage
2019-04-06 12:38:54 -07:00
6df3e57843
workaround Verilator comparaison linting
2019-04-06 02:00:47 +02:00
21b4ae8f2f
update todo, nothing todo ? everything done ?
2019-04-06 01:42:01 +02:00
e7f3dd5553
Rework CsrPlugin exception delegation
2019-04-05 23:40:39 +02:00
acaa931e11
Rework CsrPlugin interrupt delegation
2019-04-05 22:55:42 +02:00
9e72971ff0
Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin
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SUM was in fact already supported
2019-04-05 21:34:44 +02:00
82c894932a
update todolist
2019-04-05 20:04:28 +02:00
5a6665e57f
Fix DataCache flush on the last line
2019-04-05 20:02:57 +02:00
60a41bfc75
rework i$ flush
2019-04-05 18:11:10 +02:00
f5d4e745c7
Look like precise fence.i isn't required in practice
2019-04-05 18:08:25 +02:00
446e9625af
Centralised all todo in linux.scala
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Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
2019-04-05 12:17:29 +02:00
888e1c0b8a
Fix RVC instruction cache xtval allignement
2019-04-05 01:08:57 +02:00
8e6010fd71
Got the debug plugin working with the linux config (had to disable CSR ebreak)
2019-04-05 00:25:27 +02:00
4f0a02594c
Change LR/SC to reserve the whole memory
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Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
2019-04-04 20:34:35 +02:00
f8b438d9dc
cleaning
2019-04-04 12:59:08 +02:00
de1c9c6fea
Removing D$ reports
2019-04-03 14:47:00 +02:00
3f7a859e07
Got multiway I$ D$ running linux fine.
2019-04-03 14:33:35 +02:00
922c18ee49
Add data cache flush feature
2019-04-03 15:56:58 +02:00
066f562c5e
Got the MMU refilling itself with datacache cached memory access instead of io accesses
2019-04-03 14:32:21 +02:00
8be40e637b
#60 Got the new data cache design passing all tests and running linux
2019-04-02 23:44:53 +02:00
fd4da77084
#60 Got the new instruction cache design passing the standard regressions
2019-04-02 00:26:53 +02:00
bc0af02c97
#60 Got instruction cache running linux :D
2019-04-01 11:59:04 +02:00
1dff9aff8a
#60 Fix interrupt causing fetch privilege issues
2019-04-01 10:47:54 +02:00
369a3d0f5f
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
2019-03-31 23:43:56 +02:00
c7314cc606
Got buildroot login, userspace, commands working
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Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
2019-03-31 15:17:45 +02:00
de500ad8f9
Add qemu command
2019-03-30 18:29:17 +01:00
9383445e0b
Add a qemu option (wip)
2019-03-30 18:26:44 +01:00
29980016f3
#60 Fix instruction fetch exception PC by forcing LSB to be zero
2019-03-30 10:10:25 +01:00
9fff419346
Better fix
2019-03-29 09:18:44 +01:00
391cff69d3
#60 should fix the first instruction fetch privilege after interrupt
2019-03-29 09:02:44 +01:00
0c48729611
Sync impact less changes (asfar i know)
2019-03-29 08:43:15 +01:00
ad27007c3c
DBusSimplePlugin AHB bridge add hazard checking, pass tests
2019-03-28 11:41:49 +01:00
53c05c31c7
IBusSimplePlugin AHB bridge fix, pass tests
2019-03-28 10:12:42 +01:00
b0522cb491
Add AhbLite3 simulation config
2019-03-28 08:32:12 +01:00
9ac4998478
Fix emulator nested exception redirection privilege
2019-03-28 00:38:38 +01:00
ac06111163
Fix MMU MPRV, Fix emulator nested exception
2019-03-27 22:58:30 +01:00
0bed511a6c
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
2019-03-27 18:58:02 +01:00
43c3922a3d
Add prerequired stuff
2019-03-27 10:55:20 +01:00
f113946e66
Added a neutral LINUX_SOC for sim purposes
2019-03-27 10:53:41 +01:00
b69c474fa2
#60 user space reached
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/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
2019-03-27 00:26:51 +01:00
7a9f7c4fb9
Untested cacheless buses to AHB bridges
2019-03-26 16:30:53 +01:00
94fc2c3ecf
Fix some models missmatch
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Add more SBI
Add hardware LR/SC support in dbus cacheless
2019-03-26 01:25:18 +01:00
1c3fd5c38b
Fix mprv and add it into the softare model
2019-03-25 12:03:32 +01:00
1ec11dc03d
Fix mprv
2019-03-25 11:47:56 +01:00
c34f5413a3
Add MMU MPRIV for easier machinemode emulation #60
2019-03-25 10:30:13 +01:00
9d55283b3b
Machine mode emulator
2019-03-25 02:00:19 +01:00
6c0608f0dd
#60
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Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
2019-03-24 10:52:56 +01:00
ea62fd0e16
Same thing for DBusSimpleBus.
2019-03-23 23:36:13 +00:00
95c3e436dc
Make toPipelinedMemoryBus() just like the other busses
2019-03-23 22:32:48 +00:00
0656a49332
Make xtval more compliant
2019-03-23 20:12:36 +01:00
7159237104
Fix csrrs/csrrc for xip registers
2019-03-23 18:11:26 +01:00
505bff6f45
CSR Plugin now implement interruptions as specified in the spec
2019-03-23 12:56:04 +01:00
3652ede130
Add mdeleg tests
2019-03-23 11:41:10 +01:00
f7b793b7bf
Add SSTATUS.SUM/MXR feature, need testing
2019-03-22 15:49:36 +01:00
e4cdc2397a
MMU pass all test, need to and SUM and MXR and it's all ok
2019-03-22 14:52:49 +01:00
2b458fc642
Added MMU superpage support, pass MMU tests
2019-03-22 12:23:47 +01:00
af2acbd46e
Got the new MMU design to pass simple tests #60
2019-03-22 01:10:17 +01:00
7cbe399f1f
Fix some supervisor CSR access
2019-03-20 23:25:52 +01:00
39b2803914
Fix some CsrPlugin flags issues
2019-03-20 20:27:47 +01:00
6c2fe934fd
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
2019-03-20 16:27:35 +01:00
130a69eeae
Pass regressions machinemode with CSR config including Supervisor
2019-03-20 14:14:59 +01:00
d205f88fb8
riscv golden model and RTL pass all current regressions
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add RVC into the linux config
2019-03-20 12:17:43 +01:00
ccc3b63d7c
Enable golden model check for all regressions
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Need to implement missing CSR of the golden model
2019-03-20 01:12:03 +01:00
8f22365959
Disable MMU in machine mode
2019-03-19 22:21:30 +01:00
3fbc2f4458
Fix generation
2019-03-19 20:29:28 +01:00
915db9d6c9
cleaning
2019-03-18 20:50:19 +01:00
001ca45c57
Add cachless dBus IBus access right checks
2019-03-18 12:52:22 +01:00
c490838202
Added MMU support into cacheless DBus IBus plugins (for testing purposes)
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Probably full of bugs, need testing
2019-03-18 12:17:43 +01:00
ffa489d211
hardware refilled MmuPlugin wip
2019-03-17 21:06:47 +01:00
b63395435f
SimpleMul core.
2019-03-16 15:44:18 +00:00
5bc53c08ce
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple
2019-03-16 15:39:07 +00:00
bad60f39cd
Fix Decoding benchmark
2019-03-10 11:12:32 +01:00
434793711b
fix part of #59
2019-02-26 17:26:42 +01:00
e0c8ac01d2
Add custom external interrupts
2019-02-03 15:20:34 +01:00
11f55359c6
IBusCache can now avoid injectorStage in singleStage mode
2019-01-30 01:37:47 +01:00
f4598fbd0a
Add tightly coupled interface to the i$
2019-01-21 23:46:18 +01:00
b5caca54cd
restore all feature in TestsWorkspace
2019-01-16 15:25:50 +01:00
927ab6d127
Merge remote-tracking branch 'origin/master' into dev
2018-12-30 15:53:25 +01:00
dd42e30c61
Merge remote-tracking branch 'origin/master' into dev
2018-12-29 14:04:07 +01:00
d617bafb08
Roll back VexRiscvAvalonForSim to use caches
2018-12-25 00:15:23 +01:00
961abb3cf1
Avalon: Debug Clock Domain for JTAG
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This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.
See SpinalHDL/VexRiscv#48
2018-12-22 07:58:59 -08:00
76ebfb2243
Fix machine mode to supervisor delegation
2018-12-10 13:15:03 +01:00
eca54585b0
Fix hardware breakpoint
2018-12-04 16:57:24 +01:00
ac1ed40b80
Move things into SpinalHDL lib
2018-12-01 18:25:18 +01:00
Charles Papon
Tom Verbeure
Brett Foster