Dolu1990
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d2e5755df4
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revert removed code by mistake
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2018-01-31 18:29:30 +01:00 |
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Dolu1990
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30b05eaf96
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Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
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2018-01-31 18:13:42 +01:00 |
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Dolu1990
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bdbf6ecf17
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BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
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2018-01-29 14:52:31 +01:00 |
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Dolu1990
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0d318ab6b9
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Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
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2018-01-29 13:17:11 +01:00 |
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Dolu1990
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307c0b6bfa
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Now mret and ebreak are only allowed in CSR machine mode
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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93da5d29bc
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Fix dhrystone referance log
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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26732942e5
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Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
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2018-01-25 01:11:57 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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6a521a8d13
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Better MuraxSim gui
Add MuraxSim in the readme
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2018-01-09 08:59:17 +01:00 |
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Dolu1990
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9a89573942
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SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
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2018-01-06 22:09:42 +01:00 |
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Dolu1990
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43d3ffd685
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CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
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2018-01-04 17:37:23 +01:00 |
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Dolu1990
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2b7465e5df
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Add more atomic tests (PASS)
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2018-01-04 16:16:22 +01:00 |
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Dolu1990
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611f2f487f
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Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
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2018-01-04 15:24:00 +01:00 |
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Dolu1990
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4637e6cb48
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Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
add Atomic test flow
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2018-01-04 14:43:30 +01:00 |
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Dolu1990
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468dd3841e
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Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
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2018-01-04 13:16:40 +01:00 |
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Dolu1990
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4ed19f2cc5
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SpinalHDL 1.1.1
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2017-12-30 03:36:57 +01:00 |
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Dolu1990
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0d39e38906
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SpinalHDL 1.1.0
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2017-12-28 13:49:39 +01:00 |
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Dolu1990
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3c0588eb4b
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remove MuraxSim fixed path
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2017-12-19 22:33:46 +01:00 |
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Dolu1990
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7f2b2181c1
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SpinalHDL 1.0.3
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2017-12-19 21:21:16 +01:00 |
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Dolu1990
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37849b7a66
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Spinal 1.0.2 sim update
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2017-12-19 00:40:52 +01:00 |
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Dolu1990
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ebda7526b5
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MuraxSim 1.0.0
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2017-12-17 17:57:09 +01:00 |
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Dolu1990
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dda5372a6c
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Fix typo
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2017-12-14 01:05:06 +01:00 |
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Dolu1990
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d6e0761065
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Fix led gui refresh rate
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2017-12-14 01:04:31 +01:00 |
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Dolu1990
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2259c9cb0f
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Add SpinalHDL sim (1.0.0)
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2017-12-14 00:57:12 +01:00 |
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Dolu1990
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e1b86ea511
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SpinalHDL 0.11.4 update
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2017-12-01 11:19:23 +01:00 |
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Dolu1990
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586d3ed286
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Update formal VexRiscv to halt on missaligned dbus
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2017-11-26 15:30:48 +01:00 |
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Dolu1990
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4de0aac469
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Merge branch 'formal'
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2017-11-24 14:03:25 +01:00 |
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Dolu1990
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b7f4f09814
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Update verilator makefiles to support the last SpinalHDL changes (process merges)
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2017-11-21 23:56:46 +01:00 |
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Dolu1990
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9b9bbaa4ad
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Add missing full config for the iBus
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2017-11-21 00:09:02 +01:00 |
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Dolu1990
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ce6fd6d0aa
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Add VexRiscvAxi4 demo
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2017-11-20 23:57:37 +01:00 |
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Dolu1990
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7c19288648
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Update Synthesis bench
Update some synthesis results
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2017-11-17 20:10:46 +01:00 |
Tony Kao
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290dbc106e
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Fixes GPIO width mismatch
Adds explicit type to apbDecoder.slave to suppress IDE errors
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2017-11-16 15:02:13 -05:00 |
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Dolu1990
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6c3fed3505
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SpinalHDL 0.11.1
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2017-11-15 16:44:42 +01:00 |
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Dolu1990
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be3d301eaf
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Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
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2017-11-12 13:08:05 +01:00 |
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Dolu1990
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838c13d68b
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spinal.core.internals literals import
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2017-11-10 13:14:30 +01:00 |
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Dolu1990
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3060296b94
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unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
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2017-11-10 11:33:04 +01:00 |
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Dolu1990
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c3a7f4e58c
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CSR unsetRegIfNoAssignement fix
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
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2017-11-10 00:59:31 +01:00 |
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Dolu1990
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d6777ae8ec
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usetRegIfNoAssign upgrade
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2017-11-09 20:10:56 +01:00 |
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Dolu1990
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a72c7fd0d1
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Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
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2017-11-07 22:19:33 +01:00 |
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Dolu1990
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714d44d248
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Add fixed bug into the FormalPlugin comments
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2017-11-07 13:54:07 +01:00 |
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Dolu1990
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200a73bea0
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Fix FormalPlugin to pass liveness again.
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2017-11-06 23:04:33 +01:00 |
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Dolu1990
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8098a03a9b
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with no bus stall, pass all tests except uniqueness
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2017-11-06 20:26:45 +01:00 |
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Dolu1990
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e2a432eb5e
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add HaltOnExceptionPlugin
wip
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2017-11-05 20:13:27 +01:00 |
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Dolu1990
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276f7895e7
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Add FormalPlugin
Add FormalSimple CPU configuration
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2017-11-04 00:55:32 +01:00 |
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Dolu1990
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ba42f71813
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pass VexRiscv regressions
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2017-10-30 14:29:25 +01:00 |
Ubuntu
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008a5b7309
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updated main.cpp
added missing using namespace std
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2017-10-17 22:09:08 +00:00 |
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Dolu1990
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2bf7ca24f2
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Add VexRiscvAvalonWithIntegratedJtag
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2017-10-16 11:52:17 +02:00 |
Dolu1990
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aa859aae6b
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Update framework.h
Add missing using namespace std;
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2017-10-05 10:08:09 +02:00 |
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Dolu1990
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09ba7c28da
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Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
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2017-08-27 15:21:44 +02:00 |
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Dolu1990
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8168c9bf3a
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Update simd_add makefile
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2017-08-27 14:49:36 +02:00 |