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VexRiscv
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  • 7da85303dd
         Update README.md Dolu1990 2018-03-22 14:40:08 +0100
  • 351ad10925 RVC Add dhrystone regressions (PASS) Dolu1990 2018-03-21 23:36:57 +0100
  • 0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction Dolu1990 2018-03-21 22:34:54 +0100
  • 31a464ffdc VexRiscv now pass Riscv-test compressed stuff Dolu1990 2018-03-21 20:50:07 +0100
  • af638e7bde RV32IC is passing some of the compressed Riscv-test tests Dolu1990 2018-03-21 20:30:09 +0100
  • f872d599e2 Add decodePcGen Dolu1990 2018-03-20 18:34:36 +0100
  • 1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction Dolu1990 2018-03-20 00:01:28 +0100
  • ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework Dolu1990 2018-03-18 13:21:21 +0100
  • 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl Dolu1990 2018-03-15 18:56:25 +0100
  • 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings Dolu1990 2018-03-14 00:56:23 +0100
  • d9b7426cde undo InOutWrapper from Murax Dolu1990 2018-03-14 00:47:23 +0100
  • 2f8f4d5444 SpinalHDL 1.1.5 Dolu1990 2018-03-13 15:45:56 +0100
  • 7ea3e24183 update readme perf Dolu1990 2018-03-10 18:37:38 +0100
  • 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) Dolu1990 2018-03-10 13:31:35 +0100
  • f133e69fed fix readme toc Dolu1990 2018-03-10 13:04:48 +0100
  • 578e54376a Add MulDivIterativePlugin in readme Dolu1990 2018-03-10 12:57:42 +0100
  • e437a1d44e Add division support in the MulDivInterativePlugin Dolu1990 2018-03-09 22:41:47 +0100
  • 36438bd306 iterative mul improvments Dolu1990 2018-03-09 20:00:50 +0100
  • 674ab2c594 experimental iterative mul/div combo Dolu1990 2018-03-09 19:07:26 +0100
  • 5228a53293 MuraxSim improve simulation Speed Dolu1990 2018-03-06 12:20:39 +0100
  • 9b2cd7b234 MuraxSim add switch Dolu1990 2018-03-06 12:17:15 +0100
  • 53970dd284 SpinalHDL 1.1.4 Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things Dolu1990 2018-03-05 14:34:56 +0100
  • b159ccf8ed
         Update README.md Dolu1990 2018-02-27 22:43:53 +0100
  • ccad64def5 Pipeline CSR isWrite Dolu1990 2018-02-26 10:19:33 +0100
  • 2b6185b063 Decoding logic : Add primes duplication removal Dolu1990 2018-02-25 08:57:28 +0100
  • 2b6f43cef8 Fix Murax memory mapping range Dolu1990 2018-02-23 19:16:31 +0100
  • 5260ad5c35 Decoding lib cleaning Dolu1990 2018-02-20 12:19:38 +0100
  • 137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values Dolu1990 2018-02-22 22:36:13 +0100
  • d957934949 Fix ICache exception priority over miss reload Dolu1990 2018-02-19 22:44:46 +0100
  • 0270ee26fa Merge remote-tracking branch 'origin/reworkInstructionCache' Dolu1990 2018-02-18 23:52:02 +0100
  • 8ac4d72623 Update readme reworkInstructionCache Dolu1990 2018-02-18 23:48:20 +0100
  • d0e963559a Update readme with the new ICache implementation Dolu1990 2018-02-18 23:48:11 +0100
  • 93110d3b95 Add jump priority managment in PcPlugins Dolu1990 2018-02-16 14:27:20 +0100
  • 506e0e3f60 New faster/smaller/multi way instruction cache design. Single or dual stage Dolu1990 2018-02-16 02:21:08 +0100
  • 3853e0313b SynthesisBench cleaning/experiments Dolu1990 2018-02-11 14:53:42 +0100
  • 2a336c2812 update readme Dolu1990 2018-02-09 00:56:14 +0100
  • 0e6ae682b1 Add architecture section describing plugins in the readme Dolu1990 2018-02-09 00:44:27 +0100
  • 57ebfee2e6 Add more axi bridges Dolu1990 2018-02-08 21:39:22 +0100
  • fc5d89ad03
         Update README.md Dolu1990 2018-02-08 01:07:51 +0100
  • 967a0c4caf
         Update README.md Dolu1990 2018-02-08 01:01:14 +0100
  • b1bd758fd2
         Update README.md Dolu1990 2018-02-08 01:01:01 +0100
  • 3ee111e100 Update readme (gcc stuff) Dolu1990 2018-02-05 16:34:10 +0100
  • d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location Commit missing file Update dhrystone hex to use GP. 1.44 DMIPS/Mhz Dolu1990 2018-02-05 16:16:27 +0100
  • 4729e46763 Add DummyFencePlugin Dolu1990 2018-02-03 12:28:53 +0100
  • 0bc3a1a314
         Update README.md Dolu1990 2018-02-02 17:18:47 +0100
  • 3d97c1f2f2
         Update README.md Dolu1990 2018-02-02 14:47:07 +0100
  • f13dba847c Add custom csr gpio example Dolu1990 2018-02-02 11:14:55 +0100
  • b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin Dolu1990 2018-02-01 21:28:28 +0100
  • 4ee2482cbf Fix custom_csr regression against random ibus stall Dolu1990 2018-01-31 18:33:21 +0100
  • d2e5755df4 revert removed code by mistake Dolu1990 2018-01-31 18:29:30 +0100
  • 30b05eaf96 Add CsrInterface to allow custom CSR addition Add CustomCsrDemoPlugin as a show case Dolu1990 2018-01-31 18:13:42 +0100
  • 42e677ec0d 1.40 DMIPS/Mhz update Dolu1990 2018-01-29 15:24:14 +0100
  • bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions Dolu1990 2018-01-29 14:52:31 +0100
  • 0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) Add longer timeouts in the regressions tests Dolu1990 2018-01-29 13:17:11 +0100
  • 307c0b6bfa Now mret and ebreak are only allowed in CSR machine mode Dolu1990 2018-01-28 16:34:47 +0100
  • 93da5d29bc Fix dhrystone referance log Dolu1990 2018-01-28 16:32:58 +0100
  • 3f9c8edc4c
         Update README.md Dolu1990 2018-01-28 13:04:59 +0100
  • a98a0f72a6 Update GCC information, update Murax performances Dolu1990 2018-01-27 22:02:23 +0100
  • 26732942e5 Update DMIPS/Mhz Add cached config with maximal performance settings FullBarrielShifterPlugin can now be configured to do everything in the execute stage Dolu1990 2018-01-25 01:11:57 +0100
  • b3564e1b7e Fix Murax script flow (without rom file) Dolu1990 2018-01-21 15:39:10 +0100
  • 3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files Dolu1990 2018-01-20 18:29:33 +0100
  • f5d5b91f7a More info about eclipse debugging Dolu1990 2018-01-09 19:58:57 +0100
  • 6a521a8d13 Better MuraxSim gui Add MuraxSim in the readme Dolu1990 2018-01-09 08:59:17 +0100
  • 9a89573942 SpinalHDL 1.1.2 Add Murax setup with Mul Div Barriel Dolu1990 2018-01-06 22:09:42 +0100
  • 43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure Dolu1990 2018-01-04 17:37:23 +0100
  • 2b7465e5df Add more atomic tests (PASS) Dolu1990 2018-01-04 16:16:22 +0100
  • 611f2f487f Fix DataCache atomic integration into DBusCachedPlugin Atomic is passing basic tests Dolu1990 2018-01-04 15:24:00 +0100
  • 4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. add Atomic test flow Dolu1990 2018-01-04 14:43:30 +0100
  • 468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer Dolu1990 2018-01-04 13:16:40 +0100
  • 4ed19f2cc5 SpinalHDL 1.1.1 Dolu1990 2017-12-30 03:36:57 +0100
  • c3d950fb13 Clean script folder Dolu1990 2017-12-29 13:18:14 +0100
  • 0d39e38906 SpinalHDL 1.1.0 Dolu1990 2017-12-28 13:49:20 +0100
  • a4db278655
         Merge pull request #10 from Wallbraker/olimex Dolu1990 2017-12-27 22:31:33 +0100
  • 617a2948d0 Port to iCE40HX8K-EVB Jakob Bornecrantz 2017-12-27 21:21:55 +0000
  • 1b2476f217 Update to sbt 0.13.16 Dolu1990 2017-12-24 18:20:02 +0100
  • 3a913f0789 SpinalHDL 1.0.5 Dolu1990 2017-12-22 23:18:34 +0100
  • 3c0588eb4b remove MuraxSim fixed path Dolu1990 2017-12-19 22:33:46 +0100
  • 7f2b2181c1 SpinalHDL 1.0.3 Dolu1990 2017-12-19 21:21:16 +0100
  • 37849b7a66 Spinal 1.0.2 sim update Dolu1990 2017-12-19 00:40:52 +0100
  • 15463a6276 spinalhdl 1.0.1 Dolu1990 2017-12-17 19:36:18 +0100
  • f5a1793ef5 Merge remote-tracking branch 'origin/sim' Dolu1990 2017-12-17 17:57:51 +0100
  • ebda7526b5 MuraxSim 1.0.0 sim Dolu1990 2017-12-17 17:57:09 +0100
  • dda5372a6c Fix typo Dolu1990 2017-12-14 01:05:06 +0100
  • d6e0761065 Fix led gui refresh rate Dolu1990 2017-12-14 01:04:31 +0100
  • 2259c9cb0f Add SpinalHDL sim (1.0.0) Dolu1990 2017-12-14 00:57:12 +0100
  • 5a8c131eb5
         Update README.md Dolu1990 2017-12-13 13:24:43 +0100
  • 5c8251d6a7
         Update README.md Dolu1990 2017-12-13 13:23:55 +0100
  • 04ca72df66
         Update README.md Dolu1990 2017-12-05 16:29:26 +0100
  • f10dabd253 SpinalHDL 0.11.5 update Dolu1990 2017-12-05 15:58:05 +0100
  • 5402ba2917 Merge f1a50c6e0d into e1b86ea511 Dustin Richmond 2017-12-04 22:36:20 +0000
  • e1b86ea511 SpinalHDL 0.11.4 update Dolu1990 2017-12-01 11:19:23 +0100
  • 586d3ed286 Update formal VexRiscv to halt on missaligned dbus Dolu1990 2017-11-26 15:30:48 +0100
  • 4de0aac469 Merge branch 'formal' Dolu1990 2017-11-24 14:03:25 +0100
  • b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) Dolu1990 2017-11-21 23:56:46 +0100
  • 9b9bbaa4ad Add missing full config for the iBus Dolu1990 2017-11-21 00:09:02 +0100
  • ce6fd6d0aa Add VexRiscvAxi4 demo Dolu1990 2017-11-20 23:57:37 +0100
  • 7c19288648 Update Synthesis bench Update some synthesis results Dolu1990 2017-11-17 20:10:46 +0100
  • 635417aec2
         Merge pull request #9 from kaofishy/master Dolu1990 2017-11-16 21:16:53 +0100
  • 290dbc106e Fixes GPIO width mismatch Adds explicit type to apbDecoder.slave to suppress IDE errors Tony Kao 2017-11-16 15:02:13 -0500
  • 9f9ec823b8 SpinalHDL 0.11.2 Dolu1990 2017-11-15 17:57:08 +0100