5bfde29ce4
platforms/lattice_certuspro_nx_evn.py: fix led pinout
2024-08-28 17:02:05 +02:00
c5d1a252c5
targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM.
2024-08-28 15:53:53 +02:00
30e26cacac
Add sdcard and usb ohci support
2024-08-27 08:31:53 +02:00
abaa9c404c
Fix the reset
2024-08-26 18:27:55 +02:00
144462e862
add jtag
2024-08-26 18:08:09 +02:00
d2cc8ad815
Got LPDDR4 to work
2024-08-26 16:54:53 +02:00
e604745c7d
wip
2024-08-26 13:05:57 +02:00
0f8b8defb4
efinix ti375 c529 dev kit bios OK
2024-08-26 11:29:27 +02:00
4002b8167c
Merge pull request #602 from trabucayre/fix_tangPrimer20k_iostandard
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platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-19 17:14:25 +02:00
52fc033bf5
Merge pull request #599 from trabucayre/sipeed_tang_gw5A_SDRAM
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Sipeed tang gw5 a sdram
2024-08-19 17:12:48 +02:00
a5ee3c807a
platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-14 09:16:39 +02:00
b1a6da84b3
sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module
2024-08-04 12:14:56 +02:00
2fa838b79d
sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module
2024-08-04 12:13:47 +02:00
241dfb6780
fix pinnumber on connector C
2024-08-01 19:14:49 +02:00
81209b9fd1
platforms/enclustra_mercury_xu8_pe3: Revert to VivadoProgrammer since OpenFPGALoader is not albe to load bitstream correctly if FPGA is not already configured.
2024-07-22 15:28:25 +02:00
938bf8b3a6
targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
2024-07-22 15:18:27 +02:00
ab732011b3
plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints
2024-07-22 14:49:03 +02:00
5d4ebeb09c
targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe.
2024-07-22 11:40:19 +02:00
0394b626fa
platforms/enclustrat_mercury_xu8_pe3: Switch to OpenFPGALoader for loading FPGA.
2024-07-22 11:39:17 +02:00
8f8e0bd228
targets/enclustra: Add Enclustra to identifier.
2024-07-22 11:38:22 +02:00
f844d06da2
targets/litex_acorn_baseboard_mini: Add detect_ftdi_chip method since newer batch of baseboard is mounted with FTDI ft4232 chips.
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FT2232 and FT4232 chips are footprint compatible but still need to be handled differently from software.
2024-07-19 15:43:25 +02:00
6d3c87a6f7
platforms/lattice_certuspro_nx_versa: Fix default_clk.
2024-07-17 15:14:53 +02:00
fff2e6bd3f
platform: Add Lattice CertusPro-NX Versa initial support.
2024-07-17 14:53:12 +02:00
88ab3eca6f
targets: Map SPRAM to SRAM when use as SRAM.
2024-07-17 11:01:34 +02:00
524387b45d
sqrl_xcu1525: Fix typo.
2024-07-11 12:54:38 +02:00
e94e84eb16
sqrl_xcu1525: Add more QSFP IOs.
2024-07-10 18:20:01 +02:00
c7b436a202
sqrl_xcu1525: Add QSFP-0/1 ref clks and rearrange a bit naming.
2024-07-10 17:04:48 +02:00
00df115e86
sqrl_xcu1525: Add QSFP-0/1 IOs.
2024-07-10 16:44:12 +02:00
5870b078f8
platforms/xilinx_vcu118: add fmc and pmod connector pinouts
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VCU118 board has one FMC HPC, one FMC+ HSPC and two PMOD connectors,
Vivado board files does not contain pinouts for these, so pinouts are
taken from VCU118 Evaluation Board User Guide (UG1224).
Signed-off-by: Yichuan Gao <gaoyichuan000@gmail.com>
2024-07-06 00:16:53 +08:00
15c6f89b1a
#570 : Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007 .
2024-07-05 10:26:28 +02:00
2e120bf8a4
Merge pull request #570 from disdi/master
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Add support for CTUCAN for Arty & Genesys2 board
2024-07-05 09:21:09 +02:00
ac427feb0a
targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL
2024-07-03 12:36:28 +02:00
9898672744
siglent_sdr1104xe: Update IP/MAC addresses.
2024-07-02 17:09:23 +02:00
7a157d787b
lattice_certus_prox_nx: Add missing OpenFPGAALoader import.
2024-07-01 15:58:31 +02:00
1c06988d80
platforms,targets/lattice_certuspro_nx_evn,lattice_certuspro_nx_vvml: set sysconfig SPI_MASTER mode by default at platform level
2024-07-01 11:07:25 +02:00
40204ac815
Merge pull request #595 from trabucayre/lattice_certusnxpro
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Lattice certusnxpro
2024-06-28 13:26:47 +02:00
5813df9b44
Merge pull request #591 from VOGL-electronic/efinix_trion_t20_pulse_reset
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targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
2024-06-28 13:24:29 +02:00
8579af5710
lattice_certuspro_nx_vvml: new board support
2024-06-28 12:47:57 +02:00
f27bbc9645
lattice_certuspro_nx_evn: new board support
2024-06-28 12:47:16 +02:00
bd58227c86
platforms/sqrl_acorn/_litex_acorn_baseboard_mini_io: Add SFP-I2C and Debug IOs.
2024-06-27 14:55:15 +02:00
4f8540d53e
targets/litex_acorn_baseboard_mini: Switch to _litex_acorn_baseboard_mini_io.
2024-06-27 14:23:43 +02:00
91e787b5c3
platforms/sqrl_acorn: Add _litex_acorn_baseboard_mini_io for LiteX Acorn Baseboard Mini specific IOs.
2024-06-27 14:23:17 +02:00
c205bb756b
targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
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to do a reset on the trion t20 a pulse is needed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-24 09:14:55 +02:00
75ef26b8e5
platforms/machdyne_mozart_mx1.py: adding default_clk_name, default_clk_period (fix CI failure)
2024-06-22 22:43:06 +02:00
cb43cdf6f9
targets/machdyne_vanille: set uart_name to stub
2024-06-22 12:13:30 +02:00
a1df389c7e
machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
2024-06-22 11:26:43 +02:00
34e85c5cf6
machdyne: fix typos; add vanille and lakritz
2024-06-22 09:26:42 +02:00
95f5e030e5
Merge pull request #590 from trabucayre/zynq_csr_master_bus
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ZynqXXX boards: remove CSR definition and GP0 connection to CPU
2024-06-19 08:48:33 +02:00
dad6b2b9b6
efinix_trion_t20_bga256_dev_kit: Cleanup/Review platform/target.
2024-06-19 08:23:54 +02:00
8eaa4d637e
Merge pull request #589 from VOGL-electronic/sdram_efinix_trion_t20
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efinix_trion_t20: add sdram
2024-06-19 08:18:19 +02:00
70fb3de96c
targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
2024-06-19 07:59:24 +02:00
efd6c8b0aa
targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
2024-06-19 07:54:50 +02:00
07881259a5
litex_acorn_baseboard_mini: Assert cleanups.
2024-06-18 17:41:01 +02:00
6857418deb
litex_acorn_baseboard_mini: Allow simultaneous pcie and ethernet.
2024-06-18 13:56:08 +02:00
805a520b5a
litex_acorn_baseboard_mini: Fix and test PCIe Gen2 X1 with it.
2024-06-18 09:14:08 +02:00
27b99d4169
targets/lambdaconcept_ecpix5.py: allows configuring eth_ip/remote_ip/dynamic
2024-06-14 15:58:25 +02:00
635e932084
targets/lambdaconcept_ecpix5.py: added argument to select version (r02 by default)
2024-06-14 15:57:11 +02:00
6e6246d718
platforms/lambdaconcept_ecpix5.py: create_programmer: added option to select between r03 version (FT4232) and provious (FT2232)
2024-06-14 15:46:36 +02:00
1b22061e93
litex_acorn_baseboard_mini: Add PCIe support (Not yet buildable with Ethernet or SATA due to GTPE2_COMMON sharing).
2024-06-13 17:46:16 +02:00
eebe983914
platforms/sqrl_acorn: Add PCIe X1 pins when mounted in baseboard.
2024-06-13 17:23:26 +02:00
2cd89cdd16
efinix_trion_t20: add sdram
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add sdram of the efinix trion t20 bga256 dev kit.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-13 12:16:09 +02:00
ed6ff8f4fe
targets: Switch to LiteX byte size definitions.
2024-06-13 10:04:19 +02:00
1013a53240
Merge pull request #587 from akioolin/master
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Add HSEDA XC7A35T board support
2024-06-11 18:50:06 +02:00
8bb3caee5f
targets/quicklogic_quickfeather: updated qlal4s3b_cell_macro Clock and Reset signals (similar fix to #1797 )
2024-05-30 08:37:14 +02:00
3c181106b8
Add HSEDA XC7A35T board support
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Add HSEDA XC7A35T board support
2024-05-21 21:00:27 +08:00
b8d2b513a3
platforms/xilinx_zcu102.py: added PMOD0/1 (j55/j87)
2024-05-21 11:24:22 +02:00
11956b1709
platforms/xilinx_zcu106.py: added connectors and FMC HPC0/1
2024-05-17 12:16:33 +02:00
c660a7a1af
Merge pull request #585 from hansfbaier/qmtech-fgg676-fix
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qmtech_artix7_fgg676.py: This board also has a 200T variant
2024-05-16 11:09:19 +02:00
f544fec11b
Merge pull request #584 from hansfbaier/alientex_davincipro
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alientek_davincipro: fix part number
2024-05-16 11:08:14 +02:00
0b1728ce2a
platform/xilinx_zcu102: fixed FMC HP0 pinout
2024-05-14 12:12:35 +02:00
7166ef5bba
qmtech_artix7_fgg676.py: This board also has a 200T variant, and all variants are speedgrade 2
2024-05-14 08:41:05 +07:00
19bce6630d
Add initial LimeSDR XTRX Platform support (Adapted from Fairwaves XTRX).
2024-04-26 16:00:40 +02:00
7a0ee7f5cf
platforms/fairwaves_xtrx: Change rst to rst_n (active low).
2024-04-26 15:50:28 +02:00
5a25a4e2b4
alinx_axau15p: Switch to OpenFPGALoader.
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Requires: https://github.com/trabucayre/openFPGALoader/pull/452
2024-04-25 17:23:39 +02:00
f0c0005126
alientek_davincipro: fix part number
2024-04-25 07:42:19 +07:00
7cfc622353
Merge pull request #583 from hansfbaier/alientex_davincipro
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alientek davincipro: fix speedgrade
2024-04-23 15:54:33 +02:00
a6b8457111
target/efinix_ti60_f225: Add L2 Cache (16KB for now) to improve perfs/Coremark.
2024-04-23 11:45:07 +02:00
e4a15f6064
targets/alinx_axau15: Remove unwanted add_sdcard() call.
2024-04-23 11:40:01 +02:00
e0e2bf8f97
add Alientek DaVinci Pro FPGA board
2024-04-22 14:44:53 +07:00
110c051779
add Alientek DaVinci Pro FPGA board
2024-04-22 13:46:39 +07:00
aaab2dcfe2
alinx_axau15: Add PCIe speed support (Gen3 or Gen4) and add SDCard parameter.
2024-04-19 14:35:13 +02:00
3dc2fb9c0d
ti60_f225_dev_kit: Remove Ethernet/Etherbone debug that is no longer useful.
2024-04-12 12:21:36 +02:00
fad45b45c1
targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart
2024-04-11 15:12:17 +02:00
24db5783c1
adi_adrv2crr: Fix typo in PMOD pinout
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-04-10 14:06:47 +02:00
62b5b58aec
platforms,targets/xilinx_zc706: added choice between vivado(default) and openFPGALoader, re-enable DDR
2024-04-08 20:38:09 +02:00
3bd14f541e
platforms/xilinx_zc706: added missing i2c node
2024-04-05 10:47:33 +02:00
d2d38794f4
Merge pull request #579 from hansfbaier/qmtech-altera-sdram-attrs
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Better Altera SDRAM IO properties for more speed
2024-04-04 10:56:37 +02:00
cb84141cec
Merge pull request #578 from hansfbaier/qmtech-optional-core-resources
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qmtech core boards: make core resources optional
2024-04-04 10:56:02 +02:00
44ab802ae6
Merge pull request #577 from hansfbaier/qmtech-ddr3-fix
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qmtech_artix7_fgg676/fbg484: fix wrong memory chip type
2024-04-04 10:55:06 +02:00
bce119e0c3
litex_acorn_baseboard_mini: Proper fix to allow simultaneous Ethernet and SATA.
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Tested successfully with ./litex_acorn_baseboard_mini.py --with-etherbone --with-sata --build --load.
-> Able to ping 192.168.1.50
-> Able to initialize SATA:
litex> sata_init
Initialize SATA...
Model: WDC WDS120G1G0A-00SS50
Capacity: 120GB
Successful.
2024-04-04 10:52:56 +02:00
d24e69c112
litex_acorn_baseboard_mini: Try to share QPLL to allow enabling SATA and Ethernet/Etherbone simultaneously.
2024-04-03 12:04:36 +02:00
934002e7e6
targets/alinx_axau15: Avoid USPHBMPCIEPHY workaround.
2024-04-02 12:46:11 +02:00
e4c4391a9c
colorlight_i9plus: Switch to OpenFPGALoader for loading bitstreams.
2024-04-02 08:44:25 +02:00
7d89aa0fe9
qmtech altera boards: sdram io properties for more speed
2024-03-30 20:43:41 +07:00
2392473b89
targets/xilinx_zc706: typo ZCU -> ZC
2024-03-30 11:54:28 +01:00
af1cdc4ed9
qmtech core boards: make core resources optional
2024-03-30 09:59:22 +07:00
a72f2a2e68
targets/xilinx_zc706: typo...
2024-03-29 07:18:19 +01:00
27dce96bf8
targets/xilinx_zc706: SFP/etherbone working: added a note to use it
2024-03-29 07:16:53 +01:00
917ae33351
targets/xilinx_zc706: temporary disabled ddr3
2024-03-29 07:11:06 +01:00
5629f9e97a
qmtech_artix7_fgg676: fix wrong memory chip type
2024-03-29 08:41:19 +07:00
Gwenhael Goavec-Merou
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
Malte
Yichuan Gao
Fin Maaß
inc
Akio
Hans Baier
Sylvain Munaut