1261 commits

Author	SHA1	Message	Date
Florent Kermarrec	8a5b83125b	xilinx_zc706: Add Ethernet/Etherbone support through SFP/K7_1000BaseX (Untested on hardware).	2024-03-26 21:53:45 +01:00
Florent Kermarrec	a29532b5d7	xilinx_zc706: Add PCIe Gen2 X4 support (Untested on hardware).	2024-03-26 21:41:41 +01:00
Florent Kermarrec	fdd4edbd1a	xilinx_zc706: Review/Minor changes.	2024-03-26 21:35:10 +01:00
Gwenhael Goavec-Merou	6b35c47e8b	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
Florent Kermarrec	1655cbf62f	alinx_axau15: Add manual loc constraints on PCIe GTHE4 channels to avoid Vivado to remap them. ... Board now correctly seen with lspci.	2024-03-26 14:12:26 +01:00
Florent Kermarrec	cc7f092520	alinx_axau15: Fix PCIe support compilation (still needs proper instance name). ... Not yet working on hardware.	2024-03-25 19:11:33 +01:00
Florent Kermarrec	191a5bb17a	alinx_axau15: Add RGMII Ethernet/Etherbone support.	2024-03-25 16:08:38 +01:00
Gwenhael Goavec-Merou	11bf6ea703	targets/siglent_sds1104xe.py: added note on how to use crossover with jtagbone	2024-03-20 16:58:38 +01:00
AlanCui	abaa6b9a90	Rename sipeed_tang_mega_138k.py to sipeed_tang_mega_138k_pro.py	2024-03-19 17:21:21 +08:00
Florent Kermarrec	f50ee97520	alinx_axau15: Minor adjustments.	2024-03-14 15:13:59 +01:00
Florent Kermarrec	e980798437	gsd_orangecrab: Add --without_dfu_rst argument to allow disabling reset to DFU on Button press. ... This is useful in some case where were button input is force through hardware change to force DFU to be in reset at startup.	2024-03-11 17:23:42 +01:00
Florent Kermarrec	91aff9816d	targets/litex_acorn_baseboard_mini: Add with_dram parameter to allow build without DRAM.	2024-03-07 18:30:18 +01:00
enjoy-digital	8ce88ee51e	Merge pull request #569 from trabucayre/olimex_gatemate_a1_evb ... Olimex gatemate a1 evb	2024-03-05 09:38:03 +01:00
Florent Kermarrec	0b5727692f	litex_acorn_baseboard_mini: Fix imports.	2024-03-04 13:22:41 +01:00
Gwenhael Goavec-Merou	e1e989acac	Olimex GateMate A1 EVB: new Board	2024-03-02 12:23:27 +01:00
Florent Kermarrec	8b80cc1c3a	litex_acorn_baseboard_mini: Add SATA support (Gen1 and Gen2).	2024-02-29 14:36:51 +01:00
enjoy-digital	9dd246c26e	Merge pull request #567 from trabucayre/gatemate_evb ... adding colognechip_gatemate_evb	2024-02-28 17:35:48 +01:00
enjoy-digital	fab6bcf514	Merge pull request #566 from hansfbaier/qmteck-k325-fix ... Qmtech k325: fix wrong button assignment	2024-02-28 17:35:04 +01:00
Gwenhael Goavec-Merou	af09c81db6	adding colognechip_gatemate_evb	2024-02-28 17:27:21 +01:00
Hans Baier	82c0e191a7	QMTech XC7K325T: use the buttons on the core board	2024-02-28 04:40:17 +07:00
Florent Kermarrec	33a0975dd7	litex_acorn_baseboard_mini: Allow configurable sys_clk_freq with Ethernet/Etherbone.	2024-02-27 12:38:08 +01:00
Florent Kermarrec	7bc03e5fbc	targets/litex_acorn_baseboard_mini: Make it similar to other targets and keep SoC + UART + DRAM + Ethernet.	2024-02-26 17:29:09 +01:00
Florent Kermarrec	aa34acc426	targets/digilent_arty: Allow --with-ethernet and --with-etherbone and remove --with-hybrid.	2024-02-26 15:56:58 +01:00
Florent Kermarrec	feae57e7fb	target/qmtech_kintex7_devboard: +X.	2024-02-26 15:41:09 +01:00
Florent Kermarrec	23313de1b4	targets: Add initial litex_acorn_baseboard_mini target from acorn_baseboard repository.	2024-02-26 12:25:15 +01:00
Florent Kermarrec	6d07eda3c0	targets/digilent_arty: Fix indent on with_usb.	2024-02-21 10:06:49 +01:00
Florent Kermarrec	68e0453677	targets/digilent_arty: Move USB integrated to BaseSoC.	2024-02-21 09:03:53 +01:00
Florent Kermarrec	8242ab3974	targets/digilent_arty: Add Ethernet/Etherbone Hybrid mode + USB-Host (through Machyne PMOD).	2024-02-20 19:44:10 +01:00
enjoy-digital	f7c7a5a7e5	Merge pull request #563 from smunaut/adi ... Some minor updates to the ADI ADRV2CRR board	2024-02-06 16:33:53 +01:00
enjoy-digital	a6f8f0e696	Merge pull request #561 from ruurdk/qmtech ... Add support for QMTech Kintex 7 Development board	2024-02-06 16:29:54 +01:00
Sylvain Munaut	b3caabcca3	di_adrv2crr_fmc: Bump PCIe to 8 lanes ... There used to be an issue with 8 lanes litepcie USP for that board when it was first added, but it's been solved now, so might as well use all the available lanes Signed-off-by: Sylvain Munaut <tnt@246tNt.com>	2024-02-05 11:43:02 +01:00
Sylvain Munaut	2264df8a0a	adi_adrv2crr_fmc: Speedgrade of the PLL is -2 ... Speedgrade of the chip was updated in a previous commit, but I forgot to update the PLL too Signed-off-by: Sylvain Munaut <tnt@246tNt.com>	2024-02-05 11:42:14 +01:00
Ruurd Keizer	66152390ba	Add support for QMTech Kintex 7 Development board	2024-02-01 16:16:01 +01:00
John Simons	741082e5ee	Merge branch 'litex-hub:master' into axau15_update	2024-01-27 03:28:28 +01:00
John Simons	721fa0b4b3	axau15: added more FMC+ pins and made some corrrections	2024-01-27 03:27:48 +01:00
Florent Kermarrec	39dc0b36a4	sipeed_tang_mega_138k: Fix build with ethernet and local/remote ip indent.	2024-01-22 13:20:07 +01:00
Florent Kermarrec	261c61cf62	targets/sipeed_tang_nano_4k: Remove commited spiflash.o.	2024-01-14 11:24:18 +01:00
Florent Kermarrec	926d54cb41	sipeed_tang_nano_4k: Switch to LiteX's UART and expose hyperram parameter.	2024-01-11 13:54:44 +01:00
Florent Kermarrec	688a020f35	sipeed_tang_meta_138k: Add gowin_ae350 CPU initial support. ... ./sipeed_tang_mega_138k.py --cpu-type=gowin_ae350 --build --flash __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2024 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Jan 11 2024 12:37:50 BIOS CRC passed (0efaefbe) LiteX git sha1: e689aab1 --=============== SoC ==================-- CPU: Gowin AE350 @ 800MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> ident Ident: LiteX SoC on Tang Mega 138K 2024-01-11 12:37:47	2024-01-11 13:17:05 +01:00
enjoy-digital	52f9f0f107	Merge pull request #555 from machdyne/master ... add support for minze board	2024-01-07 08:10:51 +01:00
Florent Kermarrec	52aeec00d7	sipeed_tang_nano_4k: Remove note since openFPGALoader regression has been fixed.	2024-01-04 18:29:31 +01:00
Florent Kermarrec	c0a98a6b9d	targets/sipeed_tang_nano_4k: Directly integrate flashing of EMCU flash. ... Ex to build/flash bitstream + firmware with EMCU: ./sipeed_tang_nano_4k.py --cpu-type=gowin_emcu --build --flash	2024-01-03 13:07:44 +01:00
Florent Kermarrec	55ade3b2df	sipeed_tang_nano_4k: Minor cleanup/add comments.	2024-01-02 13:42:56 +01:00
inc	fd59d954ba	add support for minze board	2023-12-29 06:01:59 +01:00
Florent Kermarrec	982038508e	alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards).	2023-12-28 19:56:52 +01:00
Florent Kermarrec	e229d1a0b6	alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66.	2023-12-28 19:48:50 +01:00
enjoy-digital	b340d9e5e7	Merge pull request #550 from Johnsel/master ... alinx_axau15: Added new Alinx Artix US+ board	2023-12-28 19:24:14 +01:00
inc	754b6d2427	add support for mozart ml1	2023-12-19 22:18:21 +01:00
Gwenhael Goavec-Merou	e8bc9fa81d	targets/sipeed_tang_nano_4k: adding description to write Gowin EMCU firmware	2023-12-14 13:24:57 +01:00
John Simons	2c2b3e318a	Fixed pinout and first steps adding PCIe support	2023-12-12 15:44:51 +01:00
John Simons	ab60d91138	alinx_axau15: Fixed minor clock and sdcard reference issues	2023-12-05 21:14:57 +01:00
John Simons	7be052911b	alinx_axau15: Added new Alinx Artix US+ board	2023-12-05 20:45:57 +01:00
Florent Kermarrec	6333fbe724	targets/siglent_sds1104xe: Update with new LiteX Ethernet/Etherbone integration.	2023-11-13 09:02:09 +01:00
Florent Kermarrec	1969b4f6d3	siglent_sds1104xe: Update Ethernet/Etherbone integration.	2023-11-10 18:58:42 +01:00
Gwenhael Goavec-Merou	fd36608438	sipeed_tang_mega_138k: fix pins DRIVE, remove a[15], fix memory model	2023-11-10 07:39:19 +01:00
enjoy-digital	17a0152ef9	Merge pull request #547 from trabucayre/tangMega138k ... Tang mega138k	2023-11-09 11:56:58 +01:00
Gwenhael Goavec-Merou	4ff1362e5b	targets,platforms/sipeed_tang_mega_138k: fix copyright	2023-11-09 11:55:35 +01:00
Florent Kermarrec	8e3dc21ce5	aliexpress_xc7k70t: Review/Cleanup. ... - Cosmetic cleanups in platform. - Add clk50 constraint. - Remove JTAGBone specific support since now directly handled by LiteX.	2023-11-09 08:26:06 +01:00
Hans Baier	69ee48d421	Add AliExpress Kintex XC7K70T board	2023-11-09 10:34:18 +07:00
Gwenhael Goavec-Merou	2c52ce0c47	targets/sipeed_tang_mega_138k: fix SDRAM (requires Mister XSDS v3.0 extension)	2023-11-08 07:13:28 +01:00
Gwenhael Goavec-Merou	e9f53685fe	targets/sipeed_tang_mega_138k: DDR3 support (not working)	2023-11-08 07:00:24 +01:00
Florent Kermarrec	bc74eeca78	targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use.	2023-11-07 13:22:30 +01:00
Florent Kermarrec	c7ad9adacb	terasic_de2_115: Cosmetic cleanup.	2023-11-06 19:21:53 +01:00
enjoy-digital	d8228c2c0f	Merge pull request #544 from madprogrammer/master ... Improve terasic_de2_115 target support	2023-11-06 19:17:54 +01:00
Gwenhael Goavec-Merou	e23ac0251a	targets/sipeed_tang_mega_138k: HDMI support	2023-11-05 16:36:59 +01:00
Florent Kermarrec	8792dd8e53	target/analog_pocket: Remove debug (Will be investigated externally).	2023-10-27 15:32:36 +02:00
Sergey Anufrienko	ce951589d1	improve terasic_de2_115 target support	2023-10-23 21:15:00 +03:00
Florent Kermarrec	0d560bc240	targets/siglent_sds1104xe: Review.	2023-10-23 19:25:12 +02:00
enjoy-digital	71d8b17fff	Merge pull request #543 from trabucayre/siglent_sds1104xe_etherbone ... targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode	2023-10-23 19:20:32 +02:00
Gwenhael Goavec-Merou	26d112b094	targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode	2023-10-23 19:07:37 +02:00
Gwenhael Goavec-Merou	afbf9eb8c9	target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally	2023-10-23 17:43:13 +02:00
Gwenhael Goavec-Merou	a6f3c5276e	target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally	2023-10-23 17:16:57 +02:00
Gwenhael Goavec-Merou	a4fc45bba6	targets/efinix_titanium_ti60_f225_dev_kit: adding jtagbone support (litex_server --jtag --jtag-config openocd_titanium_ft4232.cfg)	2023-10-18 09:11:54 +02:00
Florent Kermarrec	eae62a60ac	target/analog_pocket: Fix.	2023-10-17 21:40:46 +02:00
Florent Kermarrec	cc19078650	targets/analog_pocket: Disable debug for CI.	2023-10-17 15:23:58 +02:00
Florent Kermarrec	f86ba2dea0	targets/analog_pocket: Add debug code for framebuffer (wip).	2023-10-17 13:18:07 +02:00
Gwenhael Goavec-Merou	9ae224a2a7	sipeed_tang_primer_25k: new board	2023-10-17 07:45:40 +02:00
enjoy-digital	3a75f6cf79	Merge pull request #537 from rniwase/master ... xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors, add litedram to the target.	2023-10-14 20:14:53 +02:00
rniwase	9fb388407a	targets/xilinx_zcu102: Add litedram to the target.	2023-10-14 00:00:26 +09:00
darryln	e0e8600db4	fix help text	2023-10-12 11:21:20 -04:00
Florent Kermarrec	ec2f9480b8	targets/analog_pocket: Fix indent on videophy/cores.	2023-10-09 11:59:32 +02:00
Florent Kermarrec	6386f290e9	targets/analog_pocket: Add --video-colorbars/video-terminal/video-framebuffer arguments.	2023-10-09 10:59:15 +02:00
Florent Kermarrec	dec25b7ce9	targets/analog_pocket: Add initial Video support. ... From https://github.com/tpwrules/pocket_linux.	2023-10-09 10:14:00 +02:00
Florent Kermarrec	7359a331eb	analog_pocket: Add 1:2 (HalfRate) SDRAM support.	2023-10-06 19:25:42 +02:00
Florent Kermarrec	d00810c983	sds1104xe: Fix typo.	2023-10-06 19:25:22 +02:00
Florent Kermarrec	3d7a1dd152	analog_pocket: +x.	2023-10-02 16:20:09 +02:00
Florent Kermarrec	fd6aee0250	targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman).	2023-09-27 11:06:50 +02:00
enjoy-digital	29018a8382	Merge pull request #523 from Icenowy/tangmega138k ... [RFC] sipeed_tang_mega_138k: new board	2023-09-26 19:12:44 +02:00
Florent Kermarrec	3df677cfeb	Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART. ... $ ./analog_pocket.py --uart-name=jtag_uart --build --load $ litex_term jtag --jtag-config=openocd_usb_blaster.cfg __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 21 2023 08:53:57 BIOS CRC passed (1e2b3f44) LiteX git sha1: 7d738737 --=============== SoC ==================-- CPU: VexRiscv @ 50MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 8.0KiB SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2) MAIN-RAM: 64.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 15.6MiB/s Read speed: 22.1MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>	2023-09-21 09:19:57 +02:00
Florent Kermarrec	5064c65dac	targets: Switch to openocd_usb_blaster/2.cfg.	2023-09-21 09:16:24 +02:00
Florent Kermarrec	b92c96b3a4	colorlight_i9plus: Cosmetic cleanups.	2023-08-30 17:22:11 +02:00
enjoy-digital	3471617878	Merge pull request #502 from chmousset/add_colorlight_i9plus ... [init] added colorlight i9+ based on XC7A50 FPGA	2023-08-30 16:54:26 +02:00
Florent Kermarrec	c960e85d11	targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs.	2023-08-30 09:59:23 +02:00
Florent Kermarrec	4bb064853d	targets/efinix: Update RGMII PHYs (IOs are now directly excluded in PHYs).	2023-08-30 08:56:20 +02:00
Florent Kermarrec	347b477b07	sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. ... Now passing memtest with valid reported memory size: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS CRC passed (d32a9529) LiteX git sha1: 85dadb82 --=============== SoC ==================-- CPU: VexRiscv SMP-LINUX @ 48MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64.0KiB SRAM: 6.0KiB L2: 512B SDRAM: 128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5) MAIN-RAM: 128.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |00000000| delays: - m0, b01: |00000000| delays: - m0, b02: |01100000| delays: 01+-00 m0, b03: |00000000| delays: - best: m0, b02 delays: 01+-00 m1, b00: |00000000| delays: - m1, b01: |00000000| delays: - m1, b02: |01100000| delays: 01+-00 m1, b03: |00000000| delays: - best: m1, b02 delays: 01+-00 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 11.7MiB/s Read speed: 17.4MiB/s	2023-08-29 16:50:17 +02:00
enjoy-digital	4862d0667c	Merge pull request #515 from josuah/crosslink_nx_openocd ... Allow use of OpenOCD for the Crosslink-NX	2023-08-28 16:35:20 +02:00
enjoy-digital	232e829b8f	Merge branch 'master' into crosslink_nx_main_ram	2023-08-28 16:34:27 +02:00
enjoy-digital	a9ecbffe8f	Merge pull request #520 from josuah/crosslink_nx_prog_flash ... targets/lattice_crosslink_nx_evn: fix arguments in flash programming	2023-08-28 16:33:23 +02:00
enjoy-digital	2c3d77b5be	Merge branch 'master' into crosslink_nx_spi_flash	2023-08-28 16:32:37 +02:00
Josuah Demangeon	a5a6a313cc	targets/lattice_crosslink_nx_evn: add main_ram section for firmware ... This takes the values from the Antmicro SDI MIPI converter as a model and is enough to run a Zephyr hello world, but not seemingly enough for a the Zephyr Shell sample. Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13	2023-08-18 19:56:58 +02:00