7c537748a0
colorlight_i5: Remove PRBS (too specific to application).
...
If useful for several boards, this should probably be provided directly by LiteX.
2021-03-27 09:31:48 +01:00
7737575b88
terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
2021-03-27 08:58:49 +01:00
f714e1210a
terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this.
...
The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
2021-03-27 08:56:46 +01:00
a48def1352
rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101.
2021-03-26 23:54:56 +01:00
4329a69128
sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+).
2021-03-26 23:52:36 +01:00
87df45e625
siglent_sds1104xe: Allow build without Etherbone.
2021-03-26 23:25:42 +01:00
c6ced293d4
targets/siglent_sds1104xe: Integrate VideoTerminal/VideoFrameBuffer.
2021-03-26 22:55:25 +01:00
52ded1c9aa
terasic_deca: Fix default_clk_name.
2021-03-26 22:43:40 +01:00
b54eed0859
terasic_sockit: Review/Cleanup for consistency with other boards.
2021-03-26 22:39:19 +01:00
53a767c85c
terasic_deca: Review/Cleanup for consistency with other boards.
2021-03-26 22:12:13 +01:00
be4965ca78
Merge pull request #192 from hansfbaier/deca_fixes
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terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 21:52:31 +01:00
9fea5a7fc6
targets/digilent_nexys_video: Cleanup/Simplify #191 .
2021-03-26 21:49:22 +01:00
df58639916
nexys_video: choose VADJ value with arguments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-26 14:50:05 +01:00
8c0ddd140b
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 10:46:37 +07:00
e2de69496a
targets/lattice_crossing: Avoid direct override of SoCCore.mem_map (break default SoCore.mem_map with updated imports).
2021-03-25 22:41:26 +01:00
b284fe47c3
targets/terasic_sockit: Fix compilation.
2021-03-25 19:35:44 +01:00
22f167dde4
targets/sqrl_acorn_cle_215: Add missing false path constraints.
2021-03-25 18:19:20 +01:00
7d130d6981
targets/pcie: Cleanup.
2021-03-25 17:47:06 +01:00
333fb362ca
Move import Compat directly to litex_boards.__init__.py and simplify.
2021-03-25 16:47:47 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
7633eae360
targets/colorlight_i5: Remove l2-size args (already provided by soc_core_args.
2021-03-25 14:44:52 +01:00
5253a3c43e
test/ci: Fix/Update.
2021-03-25 14:21:13 +01:00
9a45c49918
targets/versa_ecp5: Also add Vendor prefix.
2021-03-25 14:13:32 +01:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
219067ed3a
Merge pull request #190 from kazkojima/colorlight_i5-video
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colorlight_i5: Integrate Video Terminal and Video Framebuffer with ne…
2021-03-25 10:28:52 +01:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
b3786c5e52
fomu/icebreaker: Update Up5KSPRAM import (litex.soc.cores.up5kspram deprecated, still supported for now but triggers a compat notice).
2021-03-24 17:22:55 +01:00
5995769b46
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
2021-03-24 17:22:51 +01:00
cb4e00c3f2
colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-20 07:56:59 +09:00
7a1fe7a6bc
nexys4ddr: add pmod connectors, and optional sdcard on pmodd
2021-03-19 12:33:11 -04:00
6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat
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fix #848 : allow ram initialization in bitstream to enable block ram
2021-03-19 11:11:05 +01:00
ddd46205aa
ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-18 15:06:35 +01:00
4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
b7d86df01d
fix #848 : allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value
2021-03-18 08:41:19 +07:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
75f7120ff9
targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True).
2021-03-11 10:00:06 +01:00
8d3aaa8ea9
targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).
2021-03-11 09:48:26 +01:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
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Alveo U280 board
2021-03-10 11:16:32 +01:00
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x
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crosslink_nx_vip: Remove constraints for hard MIPI pins
2021-03-10 11:13:49 +01:00
61f44739d7
Merge pull request #185 from stffrdhrn/arty-jtagbone
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arty: Add an option to enable jtagbone
2021-03-10 11:12:20 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
8fb80053f7
targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
2021-03-08 17:39:13 +01:00
496cae54ff
crosslink_nx_vip: Remove constraint for MIPI pins
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:26:40 +00:00
9cdcb8cb43
ecpix5: Add Etherbone (--with-etherbone).
2021-03-08 13:45:09 +01:00
52ce49cf0c
arty: Add an option to enable jtagbone
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Then adds jtagbone for arty. I have tested with the following
litex_server and it seems to work fine.
litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg
Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.
2021-03-08 07:05:54 +09:00
6139bd7eba
Merge pull request #183 from gatecat/vip_split_mclk
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crosslink_nx_vip: Camera IO fixes
2021-03-06 11:20:53 +01:00
e280bff1ec
targets/video: Simplify/Cleanup integration.
2021-03-05 14:40:27 +01:00
ce669ac8cd
targets/nexys_video: Add optional VideoTerminal/VideoFramebuffer.
2021-03-05 14:33:22 +01:00
547157c9ca
crosslink_nx_vip: Fix cam_reset IO configuration
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:26:56 +00:00
542001dddf
crosslink_nx_vip: Split camera MCLK to its own resource
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:18:37 +00:00
21207533b0
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
2021-03-04 19:49:03 +01:00
71652e8d44
icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk.
2021-03-04 18:29:21 +01:00
253d8129af
nexys4ddr: Integrate simple VideoFrameBuffer.
2021-03-03 20:00:31 +01:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
465a95d2a6
icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.
2021-03-03 17:47:20 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
...
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
768c10c630
targets/arty: rebase/merge PR179, rename adaptor to adapter.
2021-02-25 09:36:26 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
98c80f0b2b
Merge pull request #177 from antmicro/arty-dynamic-ip
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target/arty: add eth_ip_configurable switch
2021-02-24 09:29:55 +01:00
08ccf384aa
targets/arty: Allow selection of sdcard mod adaptor
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The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
2b49082696
platforms/arty: Add numato sd card pmod
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It has a different layout.
Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817
Expansion Pin SD SPI SD Artix Arty-A7 PMOD PIN PMOD Index
2 DATA_2 D4 JD1 1 0
4 CMD MOSI D3 JD2 2 1
6 DATA_0 MISO F4 JD3 3 2
CD F3 JD4 4 3
1 DATA_3 CS_N E2 JD7 7 4
3 CLK CLK D2 JD8 8 5
5 DATA_1 H2 JD9 9 6
G2 JD10
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
ae0d4dc0d8
target/arty: add eth_dynamic_ip switch
2021-02-23 21:01:27 +01:00
aad8154e3a
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
2021-02-23 15:27:50 +01:00
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk
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fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00
a90c0bc8f9
platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope .
2021-02-22 13:45:48 +01:00
09c3bd616b
Merge branch 'master' into vc707_clk
2021-02-19 22:49:46 -08:00
c32e790421
vc707: fix default clock frequency
2021-02-19 22:47:18 -08:00
11405d9ee3
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
2021-02-18 19:30:05 +01:00
1fcd96971d
Merge pull request #172 from hansfbaier/master
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sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
2021-02-16 22:44:52 +01:00
975150ca68
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
2021-02-16 17:32:41 +01:00
9baa9d5d83
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811 ).
2021-02-12 15:23:17 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
7442c2dada
vc707.py: clk156 add missing constraint
2021-02-08 19:04:01 -08:00
fef9dd036a
platforms/de0nano: directly use JP1 connector for serial pins.
2021-02-08 09:52:26 +01:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
38242b713f
Merge pull request #171 from antmicro/symbiflow_nexys_video_support
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nexys_video: enable symbiflow toolchain
2021-02-04 16:42:34 +01:00
e6d05001aa
use parameter for dram channel 0 or 1 and LedChaser
2021-02-03 17:29:30 -05:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
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Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
8692ed462f
targets/colorlight_i5: use .bit stream instead of .svf when loading.
2021-02-03 08:17:24 +09:00
31d7f810e7
use SDRAM C1 sysclk and constraints
2021-02-02 11:15:25 -05:00
f32c61d5d2
Merge pull request #163 from garytwong/friendly-incompatible-options
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Be friendlier about incompatible options.
2021-02-02 08:51:46 +01:00
a1d830566a
added ddr4_sdram_c1 constraints
2021-02-01 12:22:41 -05:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
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./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
51c5d69586
targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
2021-02-01 13:31:56 +01:00
538878ce13
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
2021-02-01 13:31:51 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
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Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
99e2f04ee5
Be friendlier about incompatible options.
...
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
2021-01-29 18:08:38 -07:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
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Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
edb99797aa
targets/tec0117: minor cleanups.
2021-01-29 21:25:10 +01:00
345feddce9
ECPIX-5: ddram: Add missing address pin.
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Fixes #161
2021-01-29 16:03:43 +03:00
7525b8772f
platforms/fpc_iii: avoid dummy pin on ethernet.rst_n.
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rst_n is optional in LiteEth's PHYs.
2021-01-29 09:33:33 +01:00
Florent Kermarrec
Alessandro Comodi
Hans Baier
Kaz Kojima
Gabriel Somlo
gatecat
Stafford Horne
Joel Stanley
Aleksandra Swierkowska
Michael Betz
Sergiu Mosanu
Jan Kowalewski
Guillaume REMBERT
Romain Dolbeau
Gary Wong
Vadzim Dambrouski